| Paper Abstract and Keywords |
| Presentation |
2007-05-10 14:55
A Modeling of Dynamically Reconfigurable Processor using SystemC
Kouji Ueda, Junji Kitamichi, Kenichi Kuroda (The Univ. of Aidu) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
Recently, dynamically reconfigurable processors (DRPs) based on
FPGA technology are proposed.
DRPs are implemented on unique dynamically reconfigurable architecture,
and a specialized design environment is provided for the DRP.
In the case of the system design for new application specific
dynamically reconfigurable system ( DRS ), existing description language
and CAD system for existing DRA can not deal with this system design.
In this paper, we describe the system level modeling of a DRP using a
dynamic module library, which we have developed for the modeling of general
purpose DRSs at the system level.
The dynamic module library is an extended SystemC library, and enables
the modeling of the dynamically generation and elimination of modules, ports and channels
and the connection and dispatch between port and channel.
The architecture of proposed processor is based on a MIPS type architecture
and is appended
the instructions, which are for the dynamically reconfigurable operational units
and for the generation and elimination of them, and the hardware resources for the execution of appended instructions.
We describe the proposed DRP model and its simulation results. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Dynamically Reconfigurable Processor / SystemC / System Level / Modeling / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 107, pp. 19-24, May 2007. |
| Paper # |
|
| Date of Issue |
2007-05-03 (VLD) |
| ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
| Download PDF |
|
| Conference Information |
| Committee |
VLD IPSJ-SLDM |
| Conference Date |
2007-05-10 - 2007-05-11 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Kyodai Kaikan |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
System Design, etc. |
| Paper Information |
| Registration To |
IPSJ-SLDM |
| Conference Code |
2007-05-VLD-IPSJ-SLDM |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
A Modeling of Dynamically Reconfigurable Processor using SystemC |
| Sub Title (in English) |
|
| Keyword(1) |
Dynamically Reconfigurable Processor |
| Keyword(2) |
SystemC |
| Keyword(3) |
System Level |
| Keyword(4) |
Modeling |
| Keyword(5) |
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| Keyword(6) |
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| Keyword(7) |
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| Keyword(8) |
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| 1st Author's Name |
Kouji Ueda |
| 1st Author's Affiliation |
The University of Aidu (The Univ. of Aidu) |
| 2nd Author's Name |
Junji Kitamichi |
| 2nd Author's Affiliation |
The University of Aidu (The Univ. of Aidu) |
| 3rd Author's Name |
Kenichi Kuroda |
| 3rd Author's Affiliation |
The University of Aidu (The Univ. of Aidu) |
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| Speaker |
Author-2 |
| Date Time |
2007-05-10 14:55:00 |
| Presentation Time |
25 minutes |
| Registration for |
IPSJ-SLDM |
| Paper # |
VLD2007-4 |
| Volume (vol) |
vol.107 |
| Number (no) |
no.31 |
| Page |
pp.19-24 |
| #Pages |
6 |
| Date of Issue |
2007-05-03 (VLD) |
|