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| Presentation | 2007-05-31 13:15 Effect of Data Prefetching on Chip MultiProcessor Naoto Fukumoto, Tomonobu Mihara, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) Link to ES Tech. Rep. Archives:  ICD2007-20 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Chip MultiProcessors (or CMPs) can achieve higher performance by means of exploiting thread level parallelism. Increasing the number of processor cores in a chip dramatically improves the peak performance. However, since the memory bandwidth does not scale with the number of cores, the negative impact of the memory-wall problem becomes more critical. Data prefetching is a well known approach to compensating for the poor memory performance, and has been employed in commercial processor chips. Although a number of prefetching techniques have so far been proposed, in many cases, they have assumed that the processor core in a chip is only one. In CMP chips, there are some shared resources such as L2 caches, buses, and so on. Therefore, the effect of prefetching on CMPs should be different from that on single-core processors. In this paper, we analyze the effect of prefetching on CMP performance. This paper first classifies the impact of prefetch operations issued during a program execution. Then, we discuss qualitatively and quantitatively the effect of prefetching to the memory performance. The experimental results show that the negative effect of invalidation of prefetched data is very small. In addition, it is observed that about 5\% of prefetch operations improve the cache hit rates of other cores. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | CMP / data prefetching / cache memory / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, pp. 19-24, May 2007. | |
| Paper # | ||
| Date of Issue | 2007-05-24 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2007-20 |
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| Conference Information | |
| Committee | ICD IPSJ-ARC |
| Conference Date | 2007-05-31 - 2007-06-01 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Creative Collaboration between Circuit and Architecture: Processor, Memory and SOC |
| Paper Information | |
| Registration To | IPSJ-ARC |
| Conference Code | 2007-05-ICD-IPSJ-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Effect of Data Prefetching on Chip MultiProcessor |
| Sub Title (in English) | |
| Keyword(1) | CMP |
| Keyword(2) | data prefetching |
| Keyword(3) | cache memory |
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| 1st Author's Name | Naoto Fukumoto |
| 1st Author's Affiliation | Kyushu University (Kyushu Univ.) |
| 2nd Author's Name | Tomonobu Mihara |
| 2nd Author's Affiliation | Kyushu University (Kyushu Univ.) |
| 3rd Author's Name | Koji Inoue |
| 3rd Author's Affiliation | Kyushu University (Kyushu Univ.) |
| 4th Author's Name | Kazuaki Murakami |
| 4th Author's Affiliation | Kyushu University (Kyushu Univ.) |
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| Speaker | Author-1 |
| Date Time | 2007-05-31 13:15:00 |
| Presentation Time | 30 minutes |
| Registration for | IPSJ-ARC |
| Paper # | ICD2007-20 |
| Volume (vol) | vol.107 |
| Number (no) | no.76 |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2007-05-24 (ICD) |
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