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| Presentation | 2007-06-01 16:15 Design of a highly parallel VLSI processor based on functional-unit-level packet data transfer scheme Yoshichika Fujioka, Nobuhiro Tomabechi (Hachinohe Inst. Tech.), Michitaka Kameyama (Tohoku Univ.)  ICD2007-34 Link to ES Tech. Rep. Archives: ICD2007-34 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Until now, network on chip technology based on course grain packet data transfer was proposed. In this paper, fine grain packet data transfer scheme is introduced to make intra-chip data transfer flexible and programmable in micronetwork. A protocol based on hybrid utilization of autonomous packet data transfer and offline scheduling/allocation is effectively employed for making a router as simple as possible, so that packet collision in the micronetwork does not occur. Because the timing control of packet-receive is automatically done in the router, complexity of VLIW control can be greatly reduced. A special control module to control the packet-send timing is proposed to realize effective packet data transfer. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Network-on-Chip / Parallel VLSI Processor / Semi-Autonomous Packet Routing / Reduction of Control Complexity / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 76, ICD2007-34, pp. 103-108, May 2007. | |
| Paper # | ICD2007-34 | |
| Date of Issue | 2007-05-24 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ICD2007-34 Link to ES Tech. Rep. Archives: ICD2007-34 |
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| Conference Information | |
| Committee | ICD IPSJ-ARC |
| Conference Date | 2007-05-31 - 2007-06-01 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Creative Collaboration between Circuit and Architecture: Processor, Memory and SOC |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2007-05-ICD-IPSJ-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of a highly parallel VLSI processor based on functional-unit-level packet data transfer scheme |
| Sub Title (in English) | |
| Keyword(1) | Network-on-Chip |
| Keyword(2) | Parallel VLSI Processor |
| Keyword(3) | Semi-Autonomous Packet Routing |
| Keyword(4) | Reduction of Control Complexity |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Yoshichika Fujioka |
| 1st Author's Affiliation | Hachinohe Institute of Technology (Hachinohe Inst. Tech.) |
| 2nd Author's Name | Nobuhiro Tomabechi |
| 2nd Author's Affiliation | Hachinohe Institute of Technology (Hachinohe Inst. Tech.) |
| 3rd Author's Name | Michitaka Kameyama |
| 3rd Author's Affiliation | Tohoku University (Tohoku Univ.) |
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| Speaker | Author-1 |
| Date Time | 2007-06-01 16:15:00 |
| Presentation Time | 30 minutes |
| Registration for | ICD |
| Paper # | ICD2007-34 |
| Volume (vol) | vol.107 |
| Number (no) | no.76 |
| Page | pp.103-108 |
| #Pages | 6 |
| Date of Issue | 2007-05-24 (ICD) |
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