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Paper Abstract and Keywords
Presentation 2007-06-15 13:00
0.10 um Ion-Implanted GaAs MESFETs with Low Cost Production Process
Masataka Watanabe, Daiji Fukushi, Hiroshi Yano, Shigeru Nakajima (Eudyna Devices) ED2007-31
Abstract (in Japanese) (See Japanese page) 
(in English) We have successfully fabricated 0.1 µm gate GaAs MESFETs using a low cost process. The result was obtained from optical lithography, resist etching, and ion-implantation technologies based on Single Resist layer Dummy gate (SRD) process. The novel feature of the SRD process is forming a sub-quarter micron gate with conventional optical lithography. We have obtained a 0.18 µm gate using this process. Achieving a smaller gate length of 0.1um is very difficult with this process due to the pattern size shift of the sputtered SiO2 opening. In this study, we use a collimated sputtering technique in the SRD process to reduce the pattern size shift. As a result, the pattern size shift of the SiO2 opening decreases to 0.02 µm allowing a 0.1 µm gate length to be obtained by using conventional optical lithography. The high-speed performance of fT =81 GHz and an fmax of 142 GHz are achieved with the refined SRD process.
Keyword (in Japanese) (See Japanese page) 
(in English) MESFET / Ion-implantation / i-line lithography / fT / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 95, ED2007-31, pp. 1-5, June 2007.
Paper # ED2007-31 
Date of Issue 2007-06-08 (ED) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ED2007-31

Conference Information
Committee ED  
Conference Date 2007-06-15 - 2007-06-16 
Place (in Japanese) (See Japanese page) 
Place (in English) Toyama Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Compound Semiconductor Process, Device, etc 
Paper Information
Registration To ED 
Conference Code 2007-06-ED 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) 0.10 um Ion-Implanted GaAs MESFETs with Low Cost Production Process 
Sub Title (in English)  
Keyword(1) MESFET  
Keyword(2) Ion-implantation  
Keyword(3) i-line lithography  
Keyword(4) fT  
Keyword(5)  
Keyword(6)  
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1st Author's Name Masataka Watanabe  
1st Author's Affiliation Eudyna Devices Inc. (Eudyna Devices)
2nd Author's Name Daiji Fukushi  
2nd Author's Affiliation Eudyna Devices Inc. (Eudyna Devices)
3rd Author's Name Hiroshi Yano  
3rd Author's Affiliation Eudyna Devices Inc. (Eudyna Devices)
4th Author's Name Shigeru Nakajima  
4th Author's Affiliation Eudyna Devices Inc. (Eudyna Devices)
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Speaker Author-1 
Date Time 2007-06-15 13:00:00 
Presentation Time 25 minutes 
Registration for ED 
Paper # ED2007-31 
Volume (vol) vol.107 
Number (no) no.95 
Page pp.1-5 
#Pages 5 
Date of Issue 2007-06-08 (ED) 

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