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Paper Abstract and Keywords
Presentation 2007-06-22 11:30
Power Constrained IP Core Wrapper Design with Partitioned Clock Domains
Thomas Edison Yu, Tomokazu Yoneda (NAIST), Danella Zhao (Unive. of Louisiana), Hideo Fujiwara (NAIST) CAS2007-25 VLD2007-41 SIP2007-55
Abstract (in Japanese) (See Japanese page) 
(in English) Rapid developments in VLSI technology has made it possible to embed whole system components onto a single chip, called System-on-Chip or SoC. Recently, SoCs operating at multiple clock domains and very low power requirements are being utilized in the latest communications, networking and signal processing devices. Thus, the testing of SoCs and multi-clock domain embedded cores under power constraints is of great importance. This paper presents a novel design method for power-aware test wrappers targeting embedded cores with multiple clock domains. We show that effective partitioning of clock domains combined with bandwidth conversion and gated-clocks would yield shorter test times due to greater flexibility when determining optimal test schedules especially under tight power constraints.
Keyword (in Japanese) (See Japanese page) 
(in English) Multi-clock domain / Wrapper design / SoC / Embedded core test / Test scheduling / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 103, VLD2007-41, pp. 37-42, June 2007.
Paper # VLD2007-41 
Date of Issue 2007-06-15 (CAS, VLD, SIP) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CAS2007-25 VLD2007-41 SIP2007-55

Conference Information
Committee CAS SIP VLD  
Conference Date 2007-06-21 - 2007-06-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Hokkaido Tokai Univ. （Sapporo) 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2007-06-CAS-SIP-VLD 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Power Constrained IP Core Wrapper Design with Partitioned Clock Domains 
Sub Title (in English)  
Keyword(1) Multi-clock domain  
Keyword(2) Wrapper design  
Keyword(3) SoC  
Keyword(4) Embedded core test  
Keyword(5) Test scheduling  
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1st Author's Name Thomas Edison Yu  
1st Author's Affiliation Nara Institute of Science and Technology (NAIST)
2nd Author's Name Tomokazu Yoneda  
2nd Author's Affiliation Nara Institute of Science and Technology (NAIST)
3rd Author's Name Danella Zhao  
3rd Author's Affiliation University of Louisiana at Lafayette (Unive. of Louisiana)
4th Author's Name Hideo Fujiwara  
4th Author's Affiliation Nara Institute of Science and Technology (NAIST)
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Speaker Author-1 
Date Time 2007-06-22 11:30:00 
Presentation Time 20 minutes 
Registration for VLD 
Paper # CAS2007-25, VLD2007-41, SIP2007-55 
Volume (vol) vol.107 
Number (no) no.101(CAS), no.103(VLD), no.105(SIP) 
Page pp.37-42 
#Pages 6 
Date of Issue 2007-06-15 (CAS, VLD, SIP) 

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