Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2007-06-22 13:40
Optimization of Time-Multiplexed I/O Assignment in Multi-FPGA Systems
Masato Inagi, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) CAS2007-28 VLD2007-44 SIP2007-58
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, integrated circuit design size and complexity have been increasing rapidly. FPGA systems are used to
verify such large circuit designs. Due to the limitation of FPGA device capacity, multi-FPGA systems are necessary to verify state-of-the-art circuits. While a circuit must be partitioned into sub-circuits for using a multi-FPGA system, there is a problem that the number of interconnections between sub-circuits exceeds the number of I/O-pins of a FPGA when a complecated circuit is partitioned. For relaxing the shortage of I/O-pins, time-multiplexed I/O-pins, which are shared by multiple interconnections,
have been proposed. Because of their large delay, the assignment of interconnections into time-multiplexed I/O-pins highly affects the circuit performance. In this paper, we propose a integer linear programming based time-multiplexed I/O assignment optimization for a given circuit partitioning.
Keyword (in Japanese) (See Japanese page) 
(in English) prototyping / multi-FPGA / time-multiplexed I/O / integer linear programming / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 101, CAS2007-28, pp. 55-60, June 2007.
Paper # CAS2007-28 
Date of Issue 2007-06-15 (CAS, VLD, SIP) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CAS2007-28 VLD2007-44 SIP2007-58

Conference Information
Committee CAS SIP VLD  
Conference Date 2007-06-21 - 2007-06-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Hokkaido Tokai Univ. （Sapporo) 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To CAS 
Conference Code 2007-06-CAS-SIP-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Optimization of Time-Multiplexed I/O Assignment in Multi-FPGA Systems 
Sub Title (in English)  
Keyword(1) prototyping  
Keyword(2) multi-FPGA  
Keyword(3) time-multiplexed I/O  
Keyword(4) integer linear programming  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Masato Inagi  
1st Author's Affiliation The University of Kitakyushu (Univ. of Kitakyushu)
2nd Author's Name Yasuhiro Takashima  
2nd Author's Affiliation The University of Kitakyushu (Univ. of Kitakyushu)
3rd Author's Name Yuichi Nakamura  
3rd Author's Affiliation NEC Corporation (NEC)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2007-06-22 13:40:00 
Presentation Time 20 minutes 
Registration for CAS 
Paper # CAS2007-28, VLD2007-44, SIP2007-58 
Volume (vol) vol.107 
Number (no) no.101(CAS), no.103(VLD), no.105(SIP) 
Page pp.55-60 
#Pages 6 
Date of Issue 2007-06-15 (CAS, VLD, SIP) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan