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Paper Abstract and Keywords
Presentation 2007-08-23 15:00
Power Measurement for a Multiplier with Run Time Power Gating
Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Naoaki Ohkubo, Kimiyoshi Usami (S.I.T) SDM2007-152 ICD2007-80
Abstract (in Japanese) (See Japanese page) 
(in English) This paper describes a result of measurement of a Multiplier with Run Time Power Gating (RTPG). This multiplier has a scheme to dynamically reduce the leakage power according to a bit size of multiplied values. If one or both multiplied values have less than 16bit value, power gating is dynamically applied to the part of logic gates that need not to calculate output values. We design and implement this multiplier using ASPLA 90nm technology and measurement the leakage power. Experimental results show that this scheme enables to reduce the leakage power of multiplier up to 24% in the active mode, 58% in standby mode respectively at 25℃.
Keyword (in Japanese) (See Japanese page) 
(in English) MTCMOS curcuits / Dynamic Sleep Control / Leakage Power / Multiplier / Power Dissipation / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 195, ICD2007-80, pp. 63-68, Aug. 2007.
Paper # ICD2007-80 
Date of Issue 2007-08-16 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2007-152 ICD2007-80

Conference Information
Committee ICD SDM  
Conference Date 2007-08-23 - 2007-08-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitami Institute of Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Circuit and Device Technologies (High Speed, Low Voltage, and Low Power Consumption) 
Paper Information
Registration To ICD 
Conference Code 2007-08-ICD-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Power Measurement for a Multiplier with Run Time Power Gating 
Sub Title (in English)  
Keyword(1) MTCMOS curcuits  
Keyword(2) Dynamic Sleep Control  
Keyword(3) Leakage Power  
Keyword(4) Multiplier  
Keyword(5) Power Dissipation  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Toshihiro Kashima  
1st Author's Affiliation Shibaura Institute of Technology (S.I.T)
2nd Author's Name Seidai Takeda  
2nd Author's Affiliation Shibaura Institute of Technology (S.I.T)
3rd Author's Name Toshiaki Shirai  
3rd Author's Affiliation Shibaura Institute of Technology (S.I.T)
4th Author's Name Naoaki Ohkubo  
4th Author's Affiliation Shibaura Institute of Technology (S.I.T)
5th Author's Name Kimiyoshi Usami  
5th Author's Affiliation Shibaura Institute of Technology (S.I.T)
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Speaker Author-1 
Date Time 2007-08-23 15:00:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # SDM2007-152, ICD2007-80 
Volume (vol) vol.107 
Number (no) no.194(SDM), no.195(ICD) 
Page pp.63-68 
#Pages 6 
Date of Issue 2007-08-16 (SDM, ICD) 

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