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| Presentation | 2007-08-24 14:50 0.7 V SRAM Technology with Stress-Enhanced Dopant Segregated Schottky (DSS) Source/Drain Transistors for 32 nm Node Hiroyuki Onoda, Katsura Miyashita, Takeo Nakayama, Tomoko Kinoshita, Hisashi Nishimura, Atsushi Azuma, Seiji Yamada, Fumitomo Matsuoka (Toshiba)  SDM2007-165 ICD2007-93 Link to ES Tech. Rep. Archives: SDM2007-165 ICD2007-93 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | For the fist time, low supply voltage SRAM operation with stress-enhanced dopant segregated Schottky (DSS) source/drain transistors is demonstrated. At constant SRAM cell current of 40 A, we achieve two orders of magnitude lower bit-line leakage than conventional technologies at Vdd=0.7 V, while in case of constant bit-line leakage of 10 nA, supply voltage is successfully reduced down by 0.1 V. DSS technology is promising for low voltage SRAM operation for 32 nm node and beyond. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | DSS / Schottky / SRAM / 32nm / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 194, SDM2007-165, pp. 131-134, Aug. 2007. | |
| Paper # | SDM2007-165 | |
| Date of Issue | 2007-08-16 (SDM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2007-165 ICD2007-93 Link to ES Tech. Rep. Archives: SDM2007-165 ICD2007-93 |
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| Conference Information | |
| Committee | ICD SDM |
| Conference Date | 2007-08-23 - 2007-08-24 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitami Institute of Technology |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Circuit and Device Technologies (High Speed, Low Voltage, and Low Power Consumption) |
| Paper Information | |
| Registration To | SDM |
| Conference Code | 2007-08-ICD-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 0.7 V SRAM Technology with Stress-Enhanced Dopant Segregated Schottky (DSS) Source/Drain Transistors for 32 nm Node |
| Sub Title (in English) | |
| Keyword(1) | DSS |
| Keyword(2) | Schottky |
| Keyword(3) | SRAM |
| Keyword(4) | 32nm |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Hiroyuki Onoda |
| 1st Author's Affiliation | Semiconductor Company, Toshiba Corporation (Toshiba) |
| 2nd Author's Name | Katsura Miyashita |
| 2nd Author's Affiliation | Semiconductor Company, Toshiba Corporation (Toshiba) |
| 3rd Author's Name | Takeo Nakayama |
| 3rd Author's Affiliation | Semiconductor Company, Toshiba Corporation (Toshiba) |
| 4th Author's Name | Tomoko Kinoshita |
| 4th Author's Affiliation | Semiconductor Company, Toshiba Corporation (Toshiba) |
| 5th Author's Name | Hisashi Nishimura |
| 5th Author's Affiliation | Semiconductor Company, Toshiba Corporation (Toshiba) |
| 6th Author's Name | Atsushi Azuma |
| 6th Author's Affiliation | Semiconductor Company, Toshiba Corporation (Toshiba) |
| 7th Author's Name | Seiji Yamada |
| 7th Author's Affiliation | Semiconductor Company, Toshiba Corporation (Toshiba) |
| 8th Author's Name | Fumitomo Matsuoka |
| 8th Author's Affiliation | Semiconductor Company, Toshiba Corporation (Toshiba) |
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| Speaker | Author-1 |
| Date Time | 2007-08-24 14:50:00 |
| Presentation Time | 25 minutes |
| Registration for | SDM |
| Paper # | SDM2007-165, ICD2007-93 |
| Volume (vol) | vol.107 |
| Number (no) | no.194(SDM), no.195(ICD) |
| Page | pp.131-134 |
| #Pages | 4 |
| Date of Issue | 2007-08-16 (SDM, ICD) |
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