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Paper Abstract and Keywords
Presentation 2007-10-19 16:40
A Low Overhead Dependable Microcontroller Architecture with Instruction-level Rollback for Soft Error Recovery
Teruaki Sakata, Teppei Hirotsu, Hiromichi Yamada (Hitachi), Takeshi Kataoka (Renesas) R2007-45
Abstract (in Japanese) (See Japanese page) 
(in English) A low overhead, dependable microcontroller architecture has been developed. Soft errors occur in flip-flops are detected by automatic generated soft error-detecting logic circuits. After a soft error is detected, the developed rollback control module (RCM) resets the CPU and restores the CPU's register file from the backup register file using a rollback program routine. After the routine, the CPU restarts from the instruction executed before the soft error occurred. In addition, soft errors occur in RCM itself are corrected. ECC errors in RAM are corrected after error detection by the rollback architecture with no delay overheads. Testing on a 32-bit RISC microcontroller and EEMBC benchmarks showed that the area overhead was 59% and frequency overhead was 9%. In a soft error injection simulation, the MTBF was 30 times longer than those of the baseline microcontroller.
Keyword (in Japanese) (See Japanese page) 
(in English) Soft error / Rollback / ECC RAM / Mean time between failure (MTBF) / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 270, R2007-45, pp. 47-52, Oct. 2007.
Paper # R2007-45 
Date of Issue 2007-10-12 (R) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF R2007-45

Conference Information
Committee R  
Conference Date 2007-10-19 - 2007-10-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyushu University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reliability, etc. 
Paper Information
Registration To R 
Conference Code 2007-10-R 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Low Overhead Dependable Microcontroller Architecture with Instruction-level Rollback for Soft Error Recovery 
Sub Title (in English)  
Keyword(1) Soft error  
Keyword(2) Rollback  
Keyword(3) ECC RAM  
Keyword(4) Mean time between failure (MTBF)  
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1st Author's Name Teruaki Sakata  
1st Author's Affiliation Hitachi, Ltd. (Hitachi)
2nd Author's Name Teppei Hirotsu  
2nd Author's Affiliation Hitachi, Ltd. (Hitachi)
3rd Author's Name Hiromichi Yamada  
3rd Author's Affiliation Hitachi, Ltd. (Hitachi)
4th Author's Name Takeshi Kataoka  
4th Author's Affiliation Renesas Technology Corp. (Renesas)
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Speaker Author-1 
Date Time 2007-10-19 16:40:00 
Presentation Time 25 minutes 
Registration for R 
Paper # R2007-45 
Volume (vol) vol.107 
Number (no) no.270 
Page pp.47-52 
#Pages 6 
Date of Issue 2007-10-12 (R) 

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