Paper Abstract and Keywords |
Presentation |
2007-10-25 14:00
A Multiple-Chip Architecture For K-means Learning Processor Systems Yitao Ma, Tadashi Shibata (Tokyo Univ.) SIP2007-116 ICD2007-105 IE2007-75 Link to ES Tech. Rep. Archives: ICD2007-105 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Abstract
For improvement of image recognition system, a K-means processor has been developed with gravity detection architecture aiming at real time compression of feature vectors generated from input images using a 0.18-μm 5metal CMOS technology. Because of the limit of chip dimension, this processor can only process 256 feature vectors. Since we need commonly to compute about 7000 vectors for general image analysis, We proposed a multiple-chip architecture for K-means learning processor systems to solve the scalability problem. In this paper, we expound the Multiple-Chip architecture base on formerly-developed K-means processor architecture and the prototype chip designed in 0.18um 5-metal CMOS technology. |
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Reference Info. |
IEICE Tech. Rep., vol. 107, no. 287, ICD2007-105, pp. 35-40, Oct. 2007. |
Paper # |
ICD2007-105 |
Date of Issue |
2007-10-18 (SIP, ICD, IE) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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SIP2007-116 ICD2007-105 IE2007-75 Link to ES Tech. Rep. Archives: ICD2007-105 |
Conference Information |
Committee |
SIP ICD IE IPSJ-SLDM |
Conference Date |
2007-10-25 - 2007-10-26 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Aidu-Higasiyama-Onsen Kuturogijuku |
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ICD |
Conference Code |
2007-10-SIP-ICD-IE-IPSJ-SLDM |
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Japanese |
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(See Japanese page) |
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(See Japanese page) |
Title (in English) |
A Multiple-Chip Architecture For K-means Learning Processor Systems |
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1st Author's Name |
Yitao Ma |
1st Author's Affiliation |
The University of Tokyo (Tokyo Univ.) |
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Tadashi Shibata |
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The University of Tokyo (Tokyo Univ.) |
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Speaker |
Author-1 |
Date Time |
2007-10-25 14:00:00 |
Presentation Time |
20 minutes |
Registration for |
ICD |
Paper # |
SIP2007-116, ICD2007-105, IE2007-75 |
Volume (vol) |
vol.107 |
Number (no) |
no.285(SIP), no.287(ICD), no.289(IE) |
Page |
pp.35-40 |
#Pages |
6 |
Date of Issue |
2007-10-18 (SIP, ICD, IE) |
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