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Paper Abstract and Keywords
Presentation 2007-10-31 15:50
Technical Trends of Mismatch Modeling on Analog CMOS Circuit
Hiroo Masuda, Takeshi Kida, Shin-ichi Ohkawa (Renesas) VLD2007-69 SDM2007-213
Abstract (in Japanese) (See Japanese page) 
(in English) In sub-100-nm device, mismatch characteristics of threshold voltage and drain current have been degraded. This phenomenon causes variation of timing delay in digital SOC design. On the other hand, mixed signal LSI with analog circuits is expected to suffer from the mismatch-effects much compared with digital ones. This paper summarizes analog CMOS mismatch modeling activities and mismatch cancellation tequnique. We also report problems on mismatch design in future scaled low-voltage analog CMOS circuits.
Keyword (in Japanese) (See Japanese page) 
(in English) Analog CMOS / Mismatch / Modeling / Trends / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 298, SDM2007-213, pp. 47-54, Oct. 2007.
Paper # SDM2007-213 
Date of Issue 2007-10-24 (VLD, SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-69 SDM2007-213

Conference Information
Committee SDM VLD  
Conference Date 2007-10-30 - 2007-10-31 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Process, Device, Circuit Simulation, etc. 
Paper Information
Registration To SDM 
Conference Code 2007-10-SDM-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Technical Trends of Mismatch Modeling on Analog CMOS Circuit 
Sub Title (in English)  
Keyword(1) Analog CMOS  
Keyword(2) Mismatch  
Keyword(3) Modeling  
Keyword(4) Trends  
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Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Hiroo Masuda  
1st Author's Affiliation Renesas Technology Corp (Renesas)
2nd Author's Name Takeshi Kida  
2nd Author's Affiliation Renesas Technology Corp (Renesas)
3rd Author's Name Shin-ichi Ohkawa  
3rd Author's Affiliation Renesas Technology Corp (Renesas)
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Speaker Author-1 
Date Time 2007-10-31 15:50:00 
Presentation Time 25 minutes 
Registration for SDM 
Paper # VLD2007-69, SDM2007-213 
Volume (vol) vol.107 
Number (no) no.296(VLD), no.298(SDM) 
Page pp.47-54 
#Pages 8 
Date of Issue 2007-10-24 (VLD, SDM) 

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