Paper Abstract and Keywords |
Presentation |
2007-10-31 15:00
Scaled CMOS Modeling on Analog Small Signal parameters Takeshi Kida, Shin-ichi Ohkawa, Hiroo Masuda (Renesas) VLD2007-67 SDM2007-211 Link to ES Tech. Rep. Archives: SDM2007-211 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In sub-100-nm device, mismatch characteristics of threshold voltage and drain current have been degraded. This phenomenon causes variation of timing delay in digital SOC design. On the other hand, mixed signal LSI with analog circuits is expected to suffer from the mismatch-effects much compared with digital ones. This paper provides a simple expression of gm and gds for scaled CMOS, as well as their variation model. Experiments with 65-150nm CMOSs show a good agreement with new model and its variation form. This work is one of the basic characterization to proceed our mismatch modeling on analog circuit performance reported earlier. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Analog CMOS / Mismatch / Simulation and Modeling / MOS model / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 298, SDM2007-211, pp. 35-39, Oct. 2007. |
Paper # |
SDM2007-211 |
Date of Issue |
2007-10-24 (VLD, SDM) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2007-67 SDM2007-211 Link to ES Tech. Rep. Archives: SDM2007-211 |
Conference Information |
Committee |
SDM VLD |
Conference Date |
2007-10-30 - 2007-10-31 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kikai-Shinko-Kaikan Bldg. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Process, Device, Circuit Simulation, etc. |
Paper Information |
Registration To |
SDM |
Conference Code |
2007-10-SDM-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Scaled CMOS Modeling on Analog Small Signal parameters |
Sub Title (in English) |
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Keyword(1) |
Analog CMOS |
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Mismatch |
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Simulation and Modeling |
Keyword(4) |
MOS model |
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1st Author's Name |
Takeshi Kida |
1st Author's Affiliation |
Renesas Technology Corp (Renesas) |
2nd Author's Name |
Shin-ichi Ohkawa |
2nd Author's Affiliation |
Renesas Technology Corp (Renesas) |
3rd Author's Name |
Hiroo Masuda |
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Renesas Technology Corp (Renesas) |
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Speaker |
Author-2 |
Date Time |
2007-10-31 15:00:00 |
Presentation Time |
25 minutes |
Registration for |
SDM |
Paper # |
VLD2007-67, SDM2007-211 |
Volume (vol) |
vol.107 |
Number (no) |
no.296(VLD), no.298(SDM) |
Page |
pp.35-39 |
#Pages |
5 |
Date of Issue |
2007-10-24 (VLD, SDM) |
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