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Paper Abstract and Keywords
Presentation 2007-11-20 15:10
A Method for Optimizing Communication Architecture on Network-on-Chip Considering Chip Size and Wiring Costs
Daisuke Hayashi, Wataru Murai (Osaka Univ.), Akio Nakata (Hiroshima City Univ.), Tomoya Kitani, Keiichi Yasumoto (NAIST), Teruo Higashino (Osaka Univ.) CPSY2007-35
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a method for deriving an optimal Network-on-Chip (NoC) communication architecture using integer linear programming (ILP) while considering dynamic behavior of communications among processing elements (PEs).
In the proposed method, for a given chip-size constraint, the number of modules, the link delay, the set of all communication specifications and their causal dependency, and the deadline constraints for all the communications for inputs, we derive automatically an ILP problem whose optimal solution corresponds to a NoC communication architecture where the derived architecture satisfies all the deadline constraints and the
number of links is minimized. We also propose a heuristic algorithm to reduce the computation time for deriving a semi-optimal NoC communication architecture.
Keyword (in Japanese) (See Japanese page) 
(in English) Network on Chip / Deadline Constraints / Layout / Resource Optimization / Integer Linear Programming / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 333, CPSY2007-35, pp. 1-6, Nov. 2007.
Paper # CPSY2007-35 
Date of Issue 2007-11-13 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee VLD CPSY RECONF DC IPSJ-SLDM IPSJ-ARC  
Conference Date 2007-11-20 - 2007-11-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2007 ---A New Frontier in VLSI Design--- 
Paper Information
Registration To CPSY 
Conference Code 2007-11-VLD-CPSY-RECONF-DC-IPSJ-SLDM-IPSJ-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Method for Optimizing Communication Architecture on Network-on-Chip Considering Chip Size and Wiring Costs 
Sub Title (in English)  
Keyword(1) Network on Chip  
Keyword(2) Deadline Constraints  
Keyword(3) Layout  
Keyword(4) Resource Optimization  
Keyword(5) Integer Linear Programming  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Daisuke Hayashi  
1st Author's Affiliation Osaka University (Osaka Univ.)
2nd Author's Name Wataru Murai  
2nd Author's Affiliation Osaka University (Osaka Univ.)
3rd Author's Name Akio Nakata  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
4th Author's Name Tomoya Kitani  
4th Author's Affiliation NARA INSTITUTE of SCIENCE and TECHNOLOGY (NAIST)
5th Author's Name Keiichi Yasumoto  
5th Author's Affiliation NARA INSTITUTE of SCIENCE and TECHNOLOGY (NAIST)
6th Author's Name Teruo Higashino  
6th Author's Affiliation Osaka University (Osaka Univ.)
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Speaker Author-1 
Date Time 2007-11-20 15:10:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2007-35 
Volume (vol) vol.107 
Number (no) no.333 
Page pp.1-6 
#Pages 6 
Date of Issue 2007-11-13 (CPSY) 

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