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Paper Abstract and Keywords
Presentation 2007-11-20 16:00
Proposal and Circuit Performance Evaluation of Mask-less Via Programmable Device VPEX for EB Direct Writing
Masahide Kawarasaki, Akihiro Nakamura, Tomoaki Nishimoto, Yoshiaki Shitabayashi, Takeshi Fujino (Ritsumeikan Univ.) VLD2007-80 DC2007-35
Abstract (in Japanese) (See Japanese page) 
(in English) We propose the user-programmable device called VPEX (Via Programmable logic device using EXclusive-or array) which can change the logic of a digital circuit by changing two via-layer. Our novel device does not use photo-mask to change digital-circuit logic,because we use Electron Beam (EB) direct writing which is mask-less lithography. Therefore, we can cut mask cost, completely. The logic element (LE) of VPEX is composed of complex gate type EXclusive-OR (EXOR) and Inverter(INV). The single LE can outputs 12 logic functions which include all2-input logic functions by changing via-1 layer. Moreover, D-FlipFlop (DFF) consists of 5 LEs. Therefore there is no dead space unlike FPGA. In the paper, we compare performance of VPEX logic functions with that of standard-cells (Std) in 0.18μm CMOS technology. In addition, small-scale circuits of VPEX and Std are evaluated by area, delay-time and power-consumption. Finally, we discuss about comparison performance of VPEX with that of other works of via-programmable devices.
Keyword (in Japanese) (See Japanese page) 
(in English) Via-programmable device / EB direct writing / Exclusive-OR / structured ASIC / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 334, VLD2007-80, pp. 61-66, Nov. 2007.
Paper # VLD2007-80 
Date of Issue 2007-11-13 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee VLD CPSY RECONF DC IPSJ-SLDM IPSJ-ARC  
Conference Date 2007-11-20 - 2007-11-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2007 ---A New Frontier in VLSI Design--- 
Paper Information
Registration To VLD 
Conference Code 2007-11-VLD-CPSY-RECONF-DC-IPSJ-SLDM-IPSJ-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Proposal and Circuit Performance Evaluation of Mask-less Via Programmable Device VPEX for EB Direct Writing 
Sub Title (in English)  
Keyword(1) Via-programmable device  
Keyword(2) EB direct writing  
Keyword(3) Exclusive-OR  
Keyword(4) structured ASIC  
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1st Author's Name Masahide Kawarasaki  
1st Author's Affiliation Ritumeikan University (Ritsumeikan Univ.)
2nd Author's Name Akihiro Nakamura  
2nd Author's Affiliation Ritumeikan University (Ritsumeikan Univ.)
3rd Author's Name Tomoaki Nishimoto  
3rd Author's Affiliation Ritumeikan University (Ritsumeikan Univ.)
4th Author's Name Yoshiaki Shitabayashi  
4th Author's Affiliation Ritumeikan University (Ritsumeikan Univ.)
5th Author's Name Takeshi Fujino  
5th Author's Affiliation Ritumeikan University (Ritsumeikan Univ.)
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Speaker Author-1 
Date Time 2007-11-20 16:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2007-80, DC2007-35 
Volume (vol) vol.107 
Number (no) no.334(VLD), no.337(DC) 
Page pp.61-66 
#Pages
Date of Issue 2007-11-13 (VLD, DC) 


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