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Paper Abstract and Keywords
Presentation 2007-11-21 14:15
A design method for easily testable multipliers adaptable to various structures of partial product addition
Nobutaka Kito, Naofumi Takagi (Nagoya Univ.) VLD2007-83 DC2007-38
Abstract (in Japanese) (See Japanese page) 
(in English) We propose a design method for easily testable multipliers.
We construct partial product adders of a multiplier with
three types of adder blocks.
Various combinations of adder blocks lead to various structures of
partial product addition for multipliers.
A partial product generator and a final adder are also shown.
We can construct multipliers with them adaptable to various
structures of partial product addition.
These multipliers can be tested with 14 test patterns with respect to
cell fault model irrespective of its bit width.
They require 6 additional input terminals.
Keyword (in Japanese) (See Japanese page) 
(in English) design for testability / C-testability / tree multiplier / array multiplier / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 338, DC2007-38, pp. 7-12, Nov. 2007.
Paper # DC2007-38 
Date of Issue 2007-11-14 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-83 DC2007-38

Conference Information
Committee VLD CPSY RECONF DC IPSJ-SLDM IPSJ-ARC  
Conference Date 2007-11-20 - 2007-11-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2007 ---A New Frontier in VLSI Design--- 
Paper Information
Registration To DC 
Conference Code 2007-11-VLD-CPSY-RECONF-DC-IPSJ-SLDM-IPSJ-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A design method for easily testable multipliers adaptable to various structures of partial product addition 
Sub Title (in English)  
Keyword(1) design for testability  
Keyword(2) C-testability  
Keyword(3) tree multiplier  
Keyword(4) array multiplier  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Nobutaka Kito  
1st Author's Affiliation Nagoya University (Nagoya Univ.)
2nd Author's Name Naofumi Takagi  
2nd Author's Affiliation Nagoya University (Nagoya Univ.)
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Speaker Author-1 
Date Time 2007-11-21 14:15:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # VLD2007-83, DC2007-38 
Volume (vol) vol.107 
Number (no) no.335(VLD), no.338(DC) 
Page pp.7-12 
#Pages 6 
Date of Issue 2007-11-14 (VLD, DC) 

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