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Paper Abstract and Keywords
Presentation 2007-11-21 15:45
Architecture Exploration Method for Low-Power Dynamically Reconfigurable Processors
Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbungheng, Hideharu Amano (Keio Univ.) RECONF2007-40
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a design and evaluation environment for exploring the configurable dynamically reconfigurable processor arrays (DRPAs). Our template DRPA architecture is highly parameterized, and DRPA Generator can generate synthesizable RTL model of the DRPA core. In addition, our environment can provide a mixed-abstraction level simulation scheme. By exploiting this environment, the DRPA designers can efficiently explore the design space of DRPAs. Furthermore, this design environment supports novel low-power techniques including run-time power gating and dynamic voltage and frequency scaling (DVFS). In this paper, we describe the target DRPA architecture template and the RTL generation scheme of DRPA Generator. We have generated various types of DRPAs and evaluated semiconductor area and speed of them by using ASPLA/STARC 90-nm CMOS technology.
Keyword (in Japanese) (See Japanese page) 
(in English) Dynamically Reconfigurable Processors / DRPA / Configurable / RTL Generation / Architecture Exploration / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 341, RECONF2007-40, pp. 25-30, Nov. 2007.
Paper # RECONF2007-40 
Date of Issue 2007-11-14 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2007-40

Conference Information
Committee VLD CPSY RECONF DC IPSJ-SLDM IPSJ-ARC  
Conference Date 2007-11-20 - 2007-11-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2007 ---A New Frontier in VLSI Design--- 
Paper Information
Registration To RECONF 
Conference Code 2007-11-VLD-CPSY-RECONF-DC-IPSJ-SLDM-IPSJ-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Architecture Exploration Method for Low-Power Dynamically Reconfigurable Processors 
Sub Title (in English)  
Keyword(1) Dynamically Reconfigurable Processors  
Keyword(2) DRPA  
Keyword(3) Configurable  
Keyword(4) RTL Generation  
Keyword(5) Architecture Exploration  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Yohei Hasegawa  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Satoshi Tsutsumi  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Vasutan Tunbungheng  
3rd Author's Affiliation Keio University (Keio Univ.)
4th Author's Name Hideharu Amano  
4th Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2007-11-21 15:45:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2007-40 
Volume (vol) vol.107 
Number (no) no.341 
Page pp.25-30 
#Pages 6 
Date of Issue 2007-11-14 (RECONF) 

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