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Paper Abstract and Keywords
Presentation 2007-12-13 16:50
A Low Dynamic Power and Low Leakage Power 90-nm CMOS SRAM with Wide Operating Margin
Takeshi Iwanari, Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.) ICD2007-127 Link to ES Tech. Rep. Archives: ICD2007-127
Abstract (in Japanese) (See Japanese page) 
(in English) A large “write” operating margin, low-power, low leakage power 90-nm CMOS 2K-bit SRAM was fabricated incorporating a newly-developed leakage current reduction circuit called a self-controllable voltage level (SVL) circuit, a DC/DC level converter (DC/DC-C) and a forward bias (FB) circuit. A minimum “write” operating voltage of the developed SRAM was reduced to 0.3 V by the SVL circuit and was 0.4 V smaller than that of an equivalent conventional SRAM. The stand-by leakage power of the developed SRAM was only 0.34 μW, which was 3.4% that of the equivalent conventional SRAM at a VDD of 1.0V. The FB circuit decreased MOSFET threshold voltages (Vts), so that the given operating frequency (fclk) is achieved at lower VD. The DC/DC-C converted VDD=1V to VD=0.8, 0.60, 0.52, 0.38 V that were supplied to the 2K-bit SRAM. The maximum operating “Read” frequencies were 1,022 MHz, 467 MHz, 314 MHz and 85 MHz, respectively and corresponding the dynamic power of the SRAM were 3,992 μW, 1,186 μW, 655 μW and 151 μW, which were 70.9%, 40.8%, 33.4% and 25.2% of the equivalent conventional SRAM at corresponding fmaxs.
Keyword (in Japanese) (See Japanese page) 
(in English) CMOS / SRAM / leak current / power dissipation / Self-controllable Voltage Level Circuit / Forward Bias / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 382, ICD2007-127, pp. 41-46, Dec. 2007.
Paper # ICD2007-127 
Date of Issue 2007-12-06 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2007-127 Link to ES Tech. Rep. Archives: ICD2007-127

Conference Information
Committee ICD ITE-CE  
Conference Date 2007-12-13 - 2007-12-14 
Place (in Japanese) (See Japanese page) 
Place (in English)  
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Paper Information
Registration To ICD 
Conference Code 2007-12-ICD-ITE-CE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Low Dynamic Power and Low Leakage Power 90-nm CMOS SRAM with Wide Operating Margin 
Sub Title (in English)  
Keyword(1) CMOS  
Keyword(2) SRAM  
Keyword(3) leak current  
Keyword(4) power dissipation  
Keyword(5) Self-controllable Voltage Level Circuit  
Keyword(6) Forward Bias  
1st Author's Name Takeshi Iwanari  
1st Author's Affiliation Chuo University (Chuo Univ.)
2nd Author's Name Nobuaki Kobayashi  
2nd Author's Affiliation Chuo University (Chuo Univ.)
3rd Author's Name Tadayoshi Enomoto  
3rd Author's Affiliation Chuo University (Chuo Univ.)
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Speaker Author-1 
Date Time 2007-12-13 16:50:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2007-127 
Volume (vol) vol.107 
Number (no) no.382 
Page pp.41-46 
Date of Issue 2007-12-06 (ICD) 

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