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Paper Abstract and Keywords
Presentation 2007-12-14 11:35
A Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture
Masanori Hariyama, Shota Ishihara, Michitaka Kameyama (Tohoku Univ.) ICD2007-134
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents a novel asynchronous architecture
of Field-programmable gate arrays (FPGAs) to reduce
the power consumption. In the dynamic power consumption of
the conventional FPGAs, the power consumed by the switch
blocks and clock distribution is dominant since FPGAs have
complex switch blocks and the large number of registers for
high programmability. To reduce the power consumption of
switch blocks and clock distribution, asynchronous bit-serial
architecture is proposed. To ensure the correct operation independent
of data-path lengths, we use the level-encoded dualrail
encoding and propose its area-efficient implementation. The
proposed field-programmable VLSI is implemented in a 90nm
CMOS technology. The delay and the power consumption of the
proposed FPVLSI are respectively 61% and 58% of those of 4-
phase dual-rail encoding which is the most common encoding in
delay sensitive encoding.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Asynchronous Architecture / LEDR / Fine-grained architecture / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 382, ICD2007-134, pp. 83-87, Dec. 2007.
Paper # ICD2007-134 
Date of Issue 2007-12-06 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2007-134

Conference Information
Committee ICD ITE-CE  
Conference Date 2007-12-13 - 2007-12-14 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2007-12-ICD-ITE-CE 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Asynchronous Architecture  
Keyword(3) LEDR  
Keyword(4) Fine-grained architecture  
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Keyword(6)  
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1st Author's Name Masanori Hariyama  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Shota Ishihara  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Michitaka Kameyama  
3rd Author's Affiliation Tohoku University (Tohoku Univ.)
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Speaker Author-1 
Date Time 2007-12-14 11:35:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2007-134 
Volume (vol) vol.107 
Number (no) no.382 
Page pp.83-87 
#Pages 5 
Date of Issue 2007-12-06 (ICD) 

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