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Paper Abstract and Keywords
Presentation 2007-12-14 14:40
A multi matrix-processor core architecture for real-time image processing SoC
Katsuya Mizumoto, Takayuki Gyohten, Tetsushi Tanizaki, Soichi Kobayashi, Masami Nakajima, Hiroyuki Yamasaki, Hideyuki Noda, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas) ICD2007-138
Abstract (in Japanese) (See Japanese page) 
(in English) This paper describes a real time image processing SoC(MX-SoC) with programmable multi matrix -processor(MX-Core) architecture. The MX-SoC has three MX-Cores, Host-CPU, and I/O peripheral modules. An unit MX-Core is a massively parallel (1024) flexible SIMD processor based on the matrix architecture. The MX-SoC, which can perform the image processing of CCD camera, is implemented on 90nm Low Power CMOS process technology and can operate at 162MHz under the worst condition. A novel parallel pixel data processing algorism, and multi task execution suitable for multi MX-Core processing can achieve 30 Frame/sec image processing. This performance is 30 times faster than general purpose CPU solution. The MX-SoC with multi MX-Core architecture can realize the software solution of real time image processing application field.
Keyword (in Japanese) (See Japanese page) 
(in English) massively parallel processing / SIMD / processor / image processing / SoC / multi processor / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 382, ICD2007-138, pp. 107-111, Dec. 2007.
Paper # ICD2007-138 
Date of Issue 2007-12-06 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2007-138

Conference Information
Committee ICD ITE-CE  
Conference Date 2007-12-13 - 2007-12-14 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2007-12-ICD-ITE-CE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A multi matrix-processor core architecture for real-time image processing SoC 
Sub Title (in English)  
Keyword(1) massively parallel processing  
Keyword(2) SIMD  
Keyword(3) processor  
Keyword(4) image processing  
Keyword(5) SoC  
Keyword(6) multi processor  
Keyword(7)  
Keyword(8)  
1st Author's Name Katsuya Mizumoto  
1st Author's Affiliation Renesas Technology (Renesas)
2nd Author's Name Takayuki Gyohten  
2nd Author's Affiliation Renesas Technology (Renesas)
3rd Author's Name Tetsushi Tanizaki  
3rd Author's Affiliation Renesas Technology (Renesas)
4th Author's Name Soichi Kobayashi  
4th Author's Affiliation Renesas Technology (Renesas)
5th Author's Name Masami Nakajima  
5th Author's Affiliation Renesas Technology (Renesas)
6th Author's Name Hiroyuki Yamasaki  
6th Author's Affiliation Renesas Technology (Renesas)
7th Author's Name Hideyuki Noda  
7th Author's Affiliation Renesas Technology (Renesas)
8th Author's Name Motoki Higashida  
8th Author's Affiliation Renesas Technology (Renesas)
9th Author's Name Yoshihiro Okuno  
9th Author's Affiliation Renesas Technology (Renesas)
10th Author's Name Kazutami Arimoto  
10th Author's Affiliation Renesas Technology (Renesas)
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Speaker Author-1 
Date Time 2007-12-14 14:40:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2007-138 
Volume (vol) vol.107 
Number (no) no.382 
Page pp.107-111 
#Pages 5 
Date of Issue 2007-12-06 (ICD) 

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