Paper Abstract and Keywords |
Presentation |
2007-12-14 14:50
Evaluation of Hardware Algorithm Considering Wire Delay Tetsuya Nagase, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) COMP2007-51 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Computation time of hardware algorithms has been evaluated with the number of levels of the combinational circuit model. Computation time of a circuit is proportional to the number of levels of the circuit when the delay of each logic elements is a constant and the wire delay is ignored. However, in practice, the delay of logic elements depends on the wire length. In this paper, we propose a circuit model which assumes that the wire delay depends on its length. We evaluate computation time considering the wire delay by estimating the total wire delay for several hardware algorithms of parallel multiplication. As a result, we could find that computation time of multipliers which accumulate partial products in a tree structure is different from that evaluated by a traditional circuit model. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
wire delay / hardware algorithm / circuit model / parallel multiplier / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 390, COMP2007-51, pp. 23-28, Dec. 2007. |
Paper # |
COMP2007-51 |
Date of Issue |
2007-12-07 (COMP) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
COMP2007-51 |
Conference Information |
Committee |
COMP |
Conference Date |
2007-12-14 - 2007-12-14 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hiroshima University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
|
Paper Information |
Registration To |
COMP |
Conference Code |
2007-12-COMP |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Evaluation of Hardware Algorithm Considering Wire Delay |
Sub Title (in English) |
|
Keyword(1) |
wire delay |
Keyword(2) |
hardware algorithm |
Keyword(3) |
circuit model |
Keyword(4) |
parallel multiplier |
Keyword(5) |
|
Keyword(6) |
|
Keyword(7) |
|
Keyword(8) |
|
1st Author's Name |
Tetsuya Nagase |
1st Author's Affiliation |
Nagoya University (Nagoya Univ.) |
2nd Author's Name |
Kazuyoshi Takagi |
2nd Author's Affiliation |
Nagoya University (Nagoya Univ.) |
3rd Author's Name |
Naofumi Takagi |
3rd Author's Affiliation |
Nagoya University (Nagoya Univ.) |
4th Author's Name |
|
4th Author's Affiliation |
() |
5th Author's Name |
|
5th Author's Affiliation |
() |
6th Author's Name |
|
6th Author's Affiliation |
() |
7th Author's Name |
|
7th Author's Affiliation |
() |
8th Author's Name |
|
8th Author's Affiliation |
() |
9th Author's Name |
|
9th Author's Affiliation |
() |
10th Author's Name |
|
10th Author's Affiliation |
() |
11th Author's Name |
|
11th Author's Affiliation |
() |
12th Author's Name |
|
12th Author's Affiliation |
() |
13th Author's Name |
|
13th Author's Affiliation |
() |
14th Author's Name |
|
14th Author's Affiliation |
() |
15th Author's Name |
|
15th Author's Affiliation |
() |
16th Author's Name |
|
16th Author's Affiliation |
() |
17th Author's Name |
|
17th Author's Affiliation |
() |
18th Author's Name |
|
18th Author's Affiliation |
() |
19th Author's Name |
|
19th Author's Affiliation |
() |
20th Author's Name |
|
20th Author's Affiliation |
() |
Speaker |
Author-1 |
Date Time |
2007-12-14 14:50:00 |
Presentation Time |
35 minutes |
Registration for |
COMP |
Paper # |
COMP2007-51 |
Volume (vol) |
vol.107 |
Number (no) |
no.390 |
Page |
pp.23-28 |
#Pages |
6 |
Date of Issue |
2007-12-07 (COMP) |
|