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Paper Abstract and Keywords
Presentation 2008-01-16 13:20
Scalable RHPC(Reconfigurable HPC) by using FPGA array
Hiroaki Iijima, Kazuki Sato, Masatoshi Sekine (Tokyo Univ. of Agriculture and Technology) VLD2007-107 CPSY2007-50 RECONF2007-53
Abstract (in Japanese) (See Japanese page) 
(in English) PGA array that interconnect many FPGA proposed as foundation for Large-scale operations.
FPGA array we propose in this paper consist of a grid structure by using small FPGA card,
FPGA card equips with large-scale FPGA and large amount of external IO.
This FPGA can reconfigure the Arithmetic circuit to fit the target problem,
so get a dedicated circuit for high-performance computing at relatively cheap.
FPGA array aims at easy to control by embedding in the hw/sw complex through PCI type FPGA card.
This paper takes the pilot study how fast proposed system can calculate Poisson's equation by the finite difference method.
Keyword (in Japanese) (See Japanese page) 
(in English) Hardware / Software / FPGA / HPC / Simulation / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 418, RECONF2007-53, pp. 13-18, Jan. 2008.
Paper # RECONF2007-53 
Date of Issue 2008-01-09 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-107 CPSY2007-50 RECONF2007-53

Conference Information
Committee RECONF CPSY VLD IPSJ-SLDM  
Conference Date 2008-01-16 - 2008-01-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2008-01-RECONF-CPSY-VLD-IPSJ-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Scalable RHPC(Reconfigurable HPC) by using FPGA array 
Sub Title (in English)  
Keyword(1) Hardware  
Keyword(2) Software  
Keyword(3) FPGA  
Keyword(4) HPC  
Keyword(5) Simulation  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Hiroaki Iijima  
1st Author's Affiliation Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Technology)
2nd Author's Name Kazuki Sato  
2nd Author's Affiliation Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Technology)
3rd Author's Name Masatoshi Sekine  
3rd Author's Affiliation Tokyo University of Agriculture and Technology (Tokyo Univ. of Agriculture and Technology)
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Speaker Author-1 
Date Time 2008-01-16 13:20:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2007-107, CPSY2007-50, RECONF2007-53 
Volume (vol) vol.107 
Number (no) no.414(VLD), no.416(CPSY), no.418(RECONF) 
Page pp.13-18 
#Pages 6 
Date of Issue 2008-01-09 (VLD, CPSY, RECONF) 

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