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Paper Abstract and Keywords
Presentation 2008-01-16 15:35
Physical design and Evaluation of MIPS R3000 processor applying Run Time Power Gating
Toshiaki Shirai, Toshihiro Kashima, Seidai Takeda, Mitsutaka Nakata, Kimiyoshi Usami (S.I.T.), Yohei Hasegawa, Naomi Seki, Hideharu Amano (Keio Univ.) VLD2007-112 CPSY2007-55 RECONF2007-58
Abstract (in Japanese) (See Japanese page) 
(in English) Run Time Power Gating (RTPG) is a technology that reduces leakage power in a temporally/spatially fine-grained manner. This paper describes a physical design to apply RTPG to ALU, SHIFT, MULT, DIV, exception handling Coprocessor in a MIPS R3000 processor. Simulation results show that break even point to gain in power savings is 2-32 clock cycles at high temperature in 90nm technology. Delay time of ALU is increased by 16-42% by applying RTPG. Wakeup times of power-gated units are 5ns or less.
Keyword (in Japanese) (See Japanese page) 
(in English) MTCMOS circuits / Power Gating / Leakage Power / Power Dissipation / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 414, VLD2007-112, pp. 43-48, Jan. 2008.
Paper # VLD2007-112 
Date of Issue 2008-01-09 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-112 CPSY2007-55 RECONF2007-58

Conference Information
Committee RECONF CPSY VLD IPSJ-SLDM  
Conference Date 2008-01-16 - 2008-01-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To VLD 
Conference Code 2008-01-RECONF-CPSY-VLD-IPSJ-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Physical design and Evaluation of MIPS R3000 processor applying Run Time Power Gating 
Sub Title (in English)  
Keyword(1) MTCMOS circuits  
Keyword(2) Power Gating  
Keyword(3) Leakage Power  
Keyword(4) Power Dissipation  
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1st Author's Name Toshiaki Shirai  
1st Author's Affiliation Shibaura Institute of Techology (S.I.T.)
2nd Author's Name Toshihiro Kashima  
2nd Author's Affiliation Shibaura Institute of Techology (S.I.T.)
3rd Author's Name Seidai Takeda  
3rd Author's Affiliation Shibaura Institute of Techology (S.I.T.)
4th Author's Name Mitsutaka Nakata  
4th Author's Affiliation Shibaura Institute of Techology (S.I.T.)
5th Author's Name Kimiyoshi Usami  
5th Author's Affiliation Shibaura Institute of Techology (S.I.T.)
6th Author's Name Yohei Hasegawa  
6th Author's Affiliation Keio University (Keio Univ.)
7th Author's Name Naomi Seki  
7th Author's Affiliation Keio University (Keio Univ.)
8th Author's Name Hideharu Amano  
8th Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2008-01-16 15:35:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2007-112, CPSY2007-55, RECONF2007-58 
Volume (vol) vol.107 
Number (no) no.414(VLD), no.416(CPSY), no.418(RECONF) 
Page pp.43-48 
#Pages 6 
Date of Issue 2008-01-09 (VLD, CPSY, RECONF) 

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