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Paper Abstract and Keywords
Presentation 2008-01-17 16:00
A Processor Kernel Generation Method for Application Processors
Toshihiro Hiura, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2007-132 CPSY2007-75 RECONF2007-78
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes a processor kernel generation method for HW/SW co-design system named SPADES. SPADES is a system to synthesize processor cores specialized in application automatically. Low cost, small area, high performance and high productivity are required for application-specific processors in embedded systems.One of the effective methods to improve the processor performance is to integrate some hardware units such as SIMD functional units, MAC functional units, hardware loop unit, addressing unit, extra data memory, and it is important to select the appropriate hardware units depending on each target application. In our work, we divide the application-specific processor into some functional parts which are customized for additional hardware units, and our method generates and merges them. The description of the processor core is composed of each description of the function parts. In the experimental results, the VHDL descriptions of the processor cores can be generated in 3 seconds.
Keyword (in Japanese) (See Japanese page) 
(in English) Apprication-specific Processor / HDL Generation Method / HW/SW co-design / SPADES / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 415, VLD2007-132, pp. 83-88, Jan. 2008.
Paper # VLD2007-132 
Date of Issue 2008-01-10 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-132 CPSY2007-75 RECONF2007-78

Conference Information
Committee RECONF CPSY VLD IPSJ-SLDM  
Conference Date 2008-01-16 - 2008-01-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To VLD 
Conference Code 2008-01-RECONF-CPSY-VLD-IPSJ-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Processor Kernel Generation Method for Application Processors 
Sub Title (in English)  
Keyword(1) Apprication-specific Processor  
Keyword(2) HDL Generation Method  
Keyword(3) HW/SW co-design  
Keyword(4) SPADES  
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1st Author's Name Toshihiro Hiura  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Shunitsu Kohara  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Nozomu Togawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name Masao Yanagisawa  
4th Author's Affiliation Waseda University (Waseda Univ.)
5th Author's Name Tatsuo Ohtsuki  
5th Author's Affiliation Waseda University (Waseda Univ.)
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Speaker Author-1 
Date Time 2008-01-17 16:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2007-132, CPSY2007-75, RECONF2007-78 
Volume (vol) vol.107 
Number (no) no.415(VLD), no.417(CPSY), no.419(RECONF) 
Page pp.83-88 
#Pages 6 
Date of Issue 2008-01-10 (VLD, CPSY, RECONF) 

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