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Paper Abstract and Keywords
Presentation 2008-01-17 10:40
Development of Parallel Volume Rendering Accelerator VisA and its Preliminary Implementation
Takahiro Kawahara, Shinobu Miwa, Hajime Shimada (Kyoto Univ.), Shin-ichiro Mori (Univ. of Fukui), Shinji Tomita (Kyoto Univ.) VLD2007-122 CPSY2007-65 RECONF2007-68
Abstract (in Japanese) (See Japanese page) 
(in English) We are developing the parallel volume rendering accelerator VisA.VisA communicates with one-way link over DVI-D which is usualy used as a display interface, so it achieves the fine grain pipeline system which integrates both image composition between nodes and image rendering inside a node.This paper describes the design concept of VisA and its preliminary implementation.
Keyword (in Japanese) (See Japanese page) 
(in English) Visualization / Volume Rendering / Parallel Processing / FPGA / Hardware Accelerator / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 419, RECONF2007-68, pp. 25-30, Jan. 2008.
Paper # RECONF2007-68 
Date of Issue 2008-01-10 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-122 CPSY2007-65 RECONF2007-68

Conference Information
Committee RECONF CPSY VLD IPSJ-SLDM  
Conference Date 2008-01-16 - 2008-01-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2008-01-RECONF-CPSY-VLD-IPSJ-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Development of Parallel Volume Rendering Accelerator VisA and its Preliminary Implementation 
Sub Title (in English)  
Keyword(1) Visualization  
Keyword(2) Volume Rendering  
Keyword(3) Parallel Processing  
Keyword(4) FPGA  
Keyword(5) Hardware Accelerator  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Takahiro Kawahara  
1st Author's Affiliation Kyoto University (Kyoto Univ.)
2nd Author's Name Shinobu Miwa  
2nd Author's Affiliation Kyoto University (Kyoto Univ.)
3rd Author's Name Hajime Shimada  
3rd Author's Affiliation Kyoto University (Kyoto Univ.)
4th Author's Name Shin-ichiro Mori  
4th Author's Affiliation University of Fukui (Univ. of Fukui)
5th Author's Name Shinji Tomita  
5th Author's Affiliation Kyoto University (Kyoto Univ.)
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Speaker Author-1 
Date Time 2008-01-17 10:40:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2007-122, CPSY2007-65, RECONF2007-68 
Volume (vol) vol.107 
Number (no) no.415(VLD), no.417(CPSY), no.419(RECONF) 
Page pp.25-30 
#Pages 6 
Date of Issue 2008-01-10 (VLD, CPSY, RECONF) 

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