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Paper Abstract and Keywords
Presentation 2008-01-18 09:40
Arithmetic operation circuit based on abacus architecture
Syunsuke Nagasawa, Shugang Wei (Gunma Univ) CPM2007-137 ICD2007-148
Abstract (in Japanese) (See Japanese page) 
(in English) In arithmetic circuits, the carrying propagation limits the
operation speed. To shorten the length of the carrying propagation,
a lot of algorithms using hign-radix number systems have been
proposed. Calculations by the decimal number system are performed
daily, and the circuits implementation is realized by using the
binary number expression well known as BCD codes. In this paper, the
abacus architecture is introduced to achieve high speed arithmetic
circuits for the decimal number system. First we define the abacus
number representation used by the abacus architecture. Then, the
addition algorithm by the abacus number representation is described,
and the architecture of the abacus adding machine is presented. An
abacus multiplication algorithm using the abacus addition is also
proposed. Our design and expermental results show that the proposed
abacus operation machines with inputs and outputs of BCD codes are
high speed comparing to that by implementation methods based on
ordinary binary number system.
Keyword (in Japanese) (See Japanese page) 
(in English) abacus architecture / decimal addition / multiplication / BCD code / VHDL / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 426, ICD2007-148, pp. 53-58, Jan. 2008.
Paper # ICD2007-148 
Date of Issue 2008-01-10 (CPM, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPM2007-137 ICD2007-148

Conference Information
Committee CPM ICD  
Conference Date 2008-01-17 - 2008-01-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2008-01-CPM-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Arithmetic operation circuit based on abacus architecture 
Sub Title (in English)  
Keyword(1) abacus architecture  
Keyword(2) decimal addition  
Keyword(3) multiplication  
Keyword(4) BCD code  
Keyword(5) VHDL  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Syunsuke Nagasawa  
1st Author's Affiliation Gunma University (Gunma Univ)
2nd Author's Name Shugang Wei  
2nd Author's Affiliation Gunma University (Gunma Univ)
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Speaker Author-1 
Date Time 2008-01-18 09:40:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # CPM2007-137, ICD2007-148 
Volume (vol) vol.107 
Number (no) no.425(CPM), no.426(ICD) 
Page pp.53-58 
#Pages 6 
Date of Issue 2008-01-10 (CPM, ICD) 

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