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Paper Abstract and Keywords
Presentation 2008-01-25 15:45
Design and implementation of the SFQ half-precision floating point adder
Heejoung Park, Yuki Yamanashi, Kazuhiro Taketomi, Nobuyuki Yoshikawa (Yokohama National Univ.), Masamitsu Tanaka, Koji Obata, Yuki Itou, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi (Nagoya Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) A new project was started to develop a large-scale reconfigurable data-path (LSRDP) based on the single-flux-quantum (SFQ) circuits, which will be a fundamental technology for future petaflops-scale computing systems. The LSRDP is composed of a large number of floating-point units (FPUs) each of which is connected by reconfigurable routing networks. In the LSRDP, reputation loops in the source program are directly mapped to the LSRDP. The main advantage of the LSRDP is the reduction of the memory wall problem in the high-performance computing system. A memory access rate is considerably reduced, because the data are directly transferred between FPUs in the LSRDP without memory accesses.
We have studied the architecture of an SFQ floating-point adder, which is a main circuit block in the SFQ LSRDP. We have designed an SFQ floating-point adder using the SRL 2.5 kA/cm2 niobium standard process. In this study, we will show the details of the design of the SFQ floating-point adder.
Keyword (in Japanese) (See Japanese page) 
(in English) SFQ logic circuit / Floating-point adder / large-scale reconfigurable data-path / shifter / normalizer / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 458, SCE2007-31, pp. 35-40, Jan. 2008.
Paper # SCE2007-31 
Date of Issue 2008-01-18 (SCE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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Conference Information
Committee SCE  
Conference Date 2008-01-25 - 2008-01-25 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Digital applications 
Paper Information
Registration To SCE 
Conference Code 2008-01-SCE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design and implementation of the SFQ half-precision floating point adder 
Sub Title (in English)  
Keyword(1) SFQ logic circuit  
Keyword(2) Floating-point adder  
Keyword(3) large-scale reconfigurable data-path  
Keyword(4) shifter  
Keyword(5) normalizer  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Heejoung Park  
1st Author's Affiliation Yokohama National University (Yokohama National Univ.)
2nd Author's Name Yuki Yamanashi  
2nd Author's Affiliation Yokohama National University (Yokohama National Univ.)
3rd Author's Name Kazuhiro Taketomi  
3rd Author's Affiliation Yokohama National University (Yokohama National Univ.)
4th Author's Name Nobuyuki Yoshikawa  
4th Author's Affiliation Yokohama National University (Yokohama National Univ.)
5th Author's Name Masamitsu Tanaka  
5th Author's Affiliation Nagoya University (Nagoya Univ.)
6th Author's Name Koji Obata  
6th Author's Affiliation Nagoya University (Nagoya Univ.)
7th Author's Name Yuki Itou  
7th Author's Affiliation Nagoya University (Nagoya Univ.)
8th Author's Name Akira Fujimaki  
8th Author's Affiliation Nagoya University (Nagoya Univ.)
9th Author's Name Naofumi Takagi  
9th Author's Affiliation Nagoya University (Nagoya Univ.)
10th Author's Name Kazuyoshi Takagi  
10th Author's Affiliation Nagoya University (Nagoya Univ.)
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Speaker Author-1 
Date Time 2008-01-25 15:45:00 
Presentation Time 25 minutes 
Registration for SCE 
Paper # SCE2007-31 
Volume (vol) vol.107 
Number (no) no.458 
Page pp.35-40 
#Pages 6 
Date of Issue 2008-01-18 (SCE) 

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