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| Presentation | 2008-02-08 13:00 Fault Secure Property for Soft Error on FPGA Using Two-Rail Logic Takehiro Miura, Kazuteru Namba, Hideo Ito (Chiba Univ.)  DC2007-74 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In recent high-density VLSIs, soft errors frequently occur. Soft errors cause improper operation of systems. Recently, rapid product development cycle is required. So, Field Programmable Gate Arrays (FPGAs) which provide instant manufacturing are widely used. Usually, FPGAs comprise SRAMs storing configuration data. If soft errors occur on the SRAMs, configuration data are improperly changed and the system configured on the FPGA goes into wrong operation. In other words, FPGAs are sensitive to soft errors. So, soft error tolerant technologies for FPGAs are important and studied by many researchers. Two-rail logic is one of well known technologies capable of tolerating soft errors. Logic circuits constructed with two-rail logic are fault secure for single soft errors. However, it has not been discussed whether two-rail logic circuits built on FPGAs are fault secure. This paper gives evidence that two-rail logic circuits on FPGAs are fault secure for single soft errors. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FPGA / Two-rail Logic / Fault Secure / Soft Error / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 482, DC2007-74, pp. 45-50, Feb. 2008. | |
| Paper # | DC2007-74 | |
| Date of Issue | 2008-02-01 (DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2007-74 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2008-02-08 - 2008-02-08 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2008-02-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Fault Secure Property for Soft Error on FPGA Using Two-Rail Logic |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Two-rail Logic |
| Keyword(3) | Fault Secure |
| Keyword(4) | Soft Error |
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| 1st Author's Name | Takehiro Miura |
| 1st Author's Affiliation | Chiba University (Chiba Univ.) |
| 2nd Author's Name | Kazuteru Namba |
| 2nd Author's Affiliation | Chiba University (Chiba Univ.) |
| 3rd Author's Name | Hideo Ito |
| 3rd Author's Affiliation | Chiba University (Chiba Univ.) |
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| Speaker | Author-1 |
| Date Time | 2008-02-08 13:00:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2007-74 |
| Volume (vol) | vol.107 |
| Number (no) | no.482 |
| Page | pp.45-50 |
| #Pages | 6 |
| Date of Issue | 2008-02-01 (DC) |
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