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Paper Abstract and Keywords
Presentation 2008-03-07 13:00
[Poster Presentation] On a parallel architecture towards TOPS DSP built by a first-generation DSP
Bin Wu, Takao Nishitani, Hiroshi Suzuki, Hachiro Fujita (Tokyo Metro. Univ.) CAS2007-148 SIP2007-223 CS2007-113
Abstract (in Japanese) (See Japanese page) 
(in English) This paper describes the advantage of super-parallel DSP architecture [1],[2] and its implementation by FPGA. High speed processing by pipeline and VLIW generally generates useless NOP instructions, when conditional branches and jumps are executed. These NOP instructions deteriorates processor efficiency, and therefore, the system requires more power consumption. First of all, a non-pipeline DSP is introduced to the super-parallel architecture. The first generation DSP is suitable for this purpose. The system is implemented on a FPGA chip, where the original clock speed of 8MHz is employed. Recent LSI designs do not employ power supply voltage of less than 1V, due to thermal noise. Therefore, clock frequency should be set to the highest limit of non-pipeline operation for smaller size implementation, when FPGA super-parallel DSP has enough margins. The FPGA system has enough room for clock frequency under non-pipeline operation, the clock frequency is raised three times. About 300 DSPs can be equivalently mounted on a FPGA chip.
Keyword (in Japanese) (See Japanese page) 
(in English) a first-generation DSP / parallel processor / signal processing / algorithm / low power / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 527, CAS2007-148, pp. 103-104, March 2008.
Paper # CAS2007-148 
Date of Issue 2008-02-29 (CAS, SIP, CS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CAS2007-148 SIP2007-223 CS2007-113

Conference Information
Committee CS SIP CAS  
Conference Date 2008-03-06 - 2008-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English) Yamaguchi University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Network processors, signal processing for communications, wireless LAN/PAN, etc. 
Paper Information
Registration To CAS 
Conference Code 2008-03-CS-SIP-CAS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) On a parallel architecture towards TOPS DSP built by a first-generation DSP 
Sub Title (in English)  
Keyword(1) a first-generation DSP  
Keyword(2) parallel processor  
Keyword(3) signal processing  
Keyword(4) algorithm  
Keyword(5) low power  
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1st Author's Name Bin Wu  
1st Author's Affiliation Tokyo Metropolitan University (Tokyo Metro. Univ.)
2nd Author's Name Takao Nishitani  
2nd Author's Affiliation Tokyo Metropolitan University (Tokyo Metro. Univ.)
3rd Author's Name Hiroshi Suzuki  
3rd Author's Affiliation Tokyo Metropolitan University (Tokyo Metro. Univ.)
4th Author's Name Hachiro Fujita  
4th Author's Affiliation Tokyo Metropolitan University (Tokyo Metro. Univ.)
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Speaker Author-1 
Date Time 2008-03-07 13:00:00 
Presentation Time 60 minutes 
Registration for CAS 
Paper # CAS2007-148, SIP2007-223, CS2007-113 
Volume (vol) vol.107 
Number (no) no.527(CAS), no.529(SIP), no.531(CS) 
Page pp.103-104 
#Pages 2 
Date of Issue 2008-02-29 (CAS, SIP, CS) 

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