Paper Abstract and Keywords |
Presentation |
2008-03-07 16:35
New design technology of independent-Gate controlled Stacked type 3D transistor for system LSI Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-169 ICD2007-192 Link to ES Tech. Rep. Archives: ICD2007-192 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
New design technology of Independent-Gate controlled Stacked type 3D transistor has feature of Independent-gate controlled Double-Gate transistor and Stacked type 3D transistor has been proposed. Using New design technology of Independent-Gate controlled Stacked type 3D transistor, pattern area of system LSI designed by cell library can be reduced to 48% compared with that using planar MOSFET. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Independent-gate controlled Double-Gate transistor / Stacked type 3D transistor / logic circuit / system LSI / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 511, ICD2007-192, pp. 75-80, March 2008. |
Paper # |
ICD2007-192 |
Date of Issue |
2008-02-29 (VLD, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2007-169 ICD2007-192 Link to ES Tech. Rep. Archives: ICD2007-192 |
Conference Information |
Committee |
VLD ICD |
Conference Date |
2008-03-05 - 2008-03-07 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
TiRuRu |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
System-on-silicon design techniques and related VLSs |
Paper Information |
Registration To |
ICD |
Conference Code |
2008-03-VLD-ICD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
New design technology of independent-Gate controlled Stacked type 3D transistor for system LSI |
Sub Title (in English) |
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Keyword(1) |
Independent-gate controlled Double-Gate transistor |
Keyword(2) |
Stacked type 3D transistor |
Keyword(3) |
logic circuit |
Keyword(4) |
system LSI |
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1st Author's Name |
Yu Hiroshima |
1st Author's Affiliation |
Shonan Institute of Technology (Shonan Inst. of Tech.) |
2nd Author's Name |
Keisuke Okamoto |
2nd Author's Affiliation |
Shonan Institute of Technology (Shonan Inst. of Tech.) |
3rd Author's Name |
Keisuke Koizumi |
3rd Author's Affiliation |
Shonan Institute of Technology (Shonan Inst. of Tech.) |
4th Author's Name |
Shigeyoshi Watanabe |
4th Author's Affiliation |
Shonan Institute of Technology (Shonan Inst. of Tech.) |
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Speaker |
Author-1 |
Date Time |
2008-03-07 16:35:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
VLD2007-169, ICD2007-192 |
Volume (vol) |
vol.107 |
Number (no) |
no.508(VLD), no.511(ICD) |
Page |
pp.75-80 |
#Pages |
6 |
Date of Issue |
2008-02-29 (VLD, ICD) |
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