IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Nagisa Ishiura (Kwansei Gakuin Univ.)
Vice Chair Kazutoshi Wakabayashi (NEC)
Secretary Hiroyuki Ochi (Kyoto Univ.), Ichiro Kohno (Renesas)

Technical Committee on Integrated Circuits and Devices (ICD) [schedule] [select]
Chair Akira Matsuzawa (Tokyo Inst. of Tech.)
Vice Chair Kunio Uchiyama (Hitachi)
Secretary Yoshiharu Aimoto (NECEL), Makoto Nagata (Kobe Univ.)
Assistant Minoru Fujishima (Univ. of Tokyo), Yoshio Hirose (Fujitsu Labs.)

Conference Date Wed, Mar 5, 2008 13:00 - 17:10
Thu, Mar 6, 2008 09:15 - 17:00
Fri, Mar 7, 2008 09:15 - 17:25
Topics System-on-silicon design techniques and related VLSs 
Conference Place  
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Wed, Mar 5 PM 
13:00 - 15:05
(1) 13:00-13:25 Automatic synthesis and verification of practical protocol transducer based on product graph exploration VLD2007-137 ICD2007-160 Yuji Ishikawa (Univ. of Tokyo), Satoshi Komatsu, Masahiro Fujita (VDEC, Univ. of Tokyo)
(2) 13:25-13:50 Task Scheduling Technique for Mitigating SEU Vulnerability of Heterogeneous Multiprocessor Systems VLD2007-138 ICD2007-161 Makoto Sugihara (TUT)
(3) 13:50-14:15 An accurate Algorithm for RTL Power Macro-modeling VLD2007-139 ICD2007-162 Masaaki Ohtsuki, Masato Kawai, Masahiro Fukui (Ritsumeikan Univ.)
(4) 14:15-14:40 Minimizing Minimum Delay Compensations in Datapath Synthesis VLD2007-140 ICD2007-163 Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST)
(5) 14:40-15:05 An Energy-efficent ASIP Synthesis Method Based on Reducing Bit-width of Instruction Memory VLD2007-141 ICD2007-164 Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
  15:05-15:20 Break ( 15 min. )
Wed, Mar 5 PM 
15:20 - 17:10
(6) 15:20-15:45 Analog Floorplan with Soft-Module Configuration VLD2007-142 ICD2007-165 Kentarou Murata, Kazuya Sasaki, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu)
(7) 15:45-16:10 MOS Analog Module Generation VLD2007-143 ICD2007-166 Akio Fujii, Takehiko Matsuo, Toru Fujimura, Bo Yang, Shigetoshi Nakatake (Univ. of Kitakyushu)
(8) 16:10-17:10 [Fellow Memorial Lecture]
Research on VLSI Design and its Future
Hiroaki Kunieda (Tokyo Inst. Tech.)
Thu, Mar 6 AM 
09:15 - 10:55
(9) 09:15-09:40 A Design of High Accuracy and Low Power Cyclic ADC using Digital Calibration VLD2007-144 ICD2007-167 Tetsuro Ikeda, Atsushi Iwata (Hiroshima Univ.)
(10) 09:40-10:05 A-90dBm Sensitivity 0.13μm CMOS Bluetooth Transceiver Operating in Wide Temperature Range VLD2007-145 ICD2007-168 Kenichi Agawa, Hideaki Majima, Hiroyuki Kobayashi, Masayuki Koizumi, Shinichiro Ishizuka, Takeshi Nagano, Makoto Arai, Yutaka Shimizu, Go Urakawa (Toshiba)
(11) 10:05-10:30 Design and Analysis of on-chip leakage monitor using MTCMOS VLD2007-146 ICD2007-169 Satoshi Koyama, Seidai Takeda, Kimiyoshi Usami (S.I.T.)
(12) 10:30-10:55 Design and Evaluation of the component circuits for the PLL VLD2007-147 ICD2007-170 Yuko Kitaji, Masayoshi Tachibana (Kochi Univ. of Tech.)
  10:55-11:10 Break ( 15 min. )
Thu, Mar 6 AM 
11:10 - 12:25
(13) 11:10-11:35 Implementation of LCD Driver by nMOS Dynamic Logic VLD2007-148 ICD2007-171 Takuya Hachida, Hideki Matsunaka, Isao Shirakawa (Hyogo Pref. Univ.), Shuji Tsukiyama (Chuo Univ.), Masanori Hashimoto (Osaka Univ.)
(14) 11:35-12:00 A Study for Implementation of High Speed Circuit Simulator by using FPGA VLD2007-149 ICD2007-172 Taiki Hashizume, Seiji Minoura, Tadashi Mizutani, Hironobu Ishijima, Shinichi Nishizawa (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Masahiro Fukui (Ritsumeikan Univ.)
(15) 12:00-12:25 Area/Delay/Power Consumption Tradeoff for Multiplier with Tree-structured Partial-product Adders VLD2007-150 ICD2007-173 Masayoshi Tachibana (kochi University of Technology)
  12:25-13:25 Lunch Break ( 60 min. )
Thu, Mar 6 PM 
13:25 - 15:30
(16) 13:25-14:15 [Invited Talk]
Self descriptive verfication in Continuation based C and it's application to Cell architecture
Shinji Kono (University of the Ryukyus)
(17) 14:15-14:40 Conversion to CbC which used the Cell architecture from C Akira Kamizato, Shinji Kono (Univ of ryukyu)
(18) 14:40-15:05 A Case Study on MPEG4 Decoder Design with SystemBuilder VLD2007-151 ICD2007-174 Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.)
(19) 15:05-15:30 Performance Estimation considering False-paths for System-level Design VLD2007-152 ICD2007-175 Daisuke Ando, Takeshi Matsumoto, Tasuku Nishihara, Masahiro Fujita (Univ. of Tokyo)
  15:30-15:45 Break ( 15 min. )
Thu, Mar 6 PM 
15:45 - 17:00
(20) 15:45-16:10 Superposition Effect Validation of Inductive Coupling Noise Based on Measurement of Interconnect Delay Variation VLD2007-153 ICD2007-176 Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye (Osaka Univ.)
(21) 16:10-16:35 Global Routing Method of Plating Lead for 2-Layer BGA Packages VLD2007-154 ICD2007-177 Naoki Sato, Yoichi Tomioka, Atsushi Takahashi (Tokyo Tech)
(22) 16:35-17:00 Comparison of Power consumption between dynamic voltage scheme and multi-supply voltage scheme for system LSI VLD2007-155 ICD2007-178 Satoshi Hanami, Shigeyoshi Watanabe (Shonan Inst. of Tech.)
Fri, Mar 7 AM 
09:15 - 10:30
(23) 09:15-09:40 A delay balancing technique for wave-pipelining VLD2007-156 ICD2007-179 Keiichiro Sano, Jubee Tada (Yamagata Univ), Ryusuke Egawa (Touhoku Univ), Gensuke Goto (Yamagata Univ)
(24) 09:40-10:05 Enhancing Multimedia Processing by Wave-Pipelining a Multifunctional Execution Unit VLD2007-157 ICD2007-180 Kazunori Noda, Atuko Yokoyama, Hiroki Takeda, Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.)
(25) 10:05-10:30 A Self-timed Processor with Dynamic Voltage Scaling VLD2007-158 ICD2007-181 Taku Sogabe, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo)
  10:30-10:45 Break ( 15 min. )
Fri, Mar 7 AM 
10:45 - 12:00
(26) 10:45-11:10 A High-Throughput Architectures for LDPC Coded OFDM Baseband Processor VLD2007-159 ICD2007-182 Shinsuke Ushiki, Koichi Nakamura, Kazunori Shimizu, Qi Wang, Yuta Abe, Satoshi Goto, Takeshi Ikenaga (Waseda Univ.)
(27) 11:10-11:35 Design of High-rate Irregular LDPC Decoder based on Accelerated Message-passing Schedule VLD2007-160 ICD2007-183 Yuta Abe, Naoki Tajima, Xing Li, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.)
(28) 11:35-12:00 Low Power Design of Accelerated Message-Passing LDPC Decoder for Long Codes Naoki Tajima, Yuta Abe, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.)
  12:00-13:00 Lunch Break ( 60 min. )
Fri, Mar 7 PM 
13:00 - 15:05
(29) 13:00-13:25 The Improvement of the Ubiqitus Processor HCgorilla VLD2007-161 ICD2007-184 Hiroki Takeda, Kazunori Noda, Atuko Yokoyama, Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ)
(30) 13:25-13:50 An adaptive error concealment order H.264/AVC VLD2007-162 ICD2007-185 Jun Wang, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.)
(31) 13:50-14:15 A Low-cost Speed and Yield Enhancement Method Using Embedded Delay Detectors on FPGAs VLD2007-163 ICD2007-186 Yohei Kume, Yuuri Sugihara, Ngo Cam Lai, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.)
(32) 14:15-14:40 Application-Oriented Dynamic Reconfigurable Network Processor Architecture and Its Optimization Method VLD2007-164 ICD2007-187 Motonori Ohta, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ)
(33) 14:40-15:05 Implementation and Evaluation of Network Security using An Embedded Programmable Logic Matrix (ePLX) VLD2007-165 ICD2007-188 Mitsutaka Matsumoto, Shun Kimura (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology Corp.), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.)
  15:05-15:20 Break ( 15 min. )
Fri, Mar 7 PM 
15:20 - 17:25
(34) 15:20-15:45 An Object Oriented System LSI Design Methodology and Its Evaluation VLD2007-166 ICD2007-189 Takafumi Kohara, Hiroyuki Terai, Seigo Masuoka (Kinki University), Akihisa Yamada (SHARP Corp.), Takashi Kambe (Kinki University)
(35) 15:45-16:10 A Circuit Design of Reed-Solomon Decoder using Dynamically Reconfigurable Processor VLD2007-167 ICD2007-190 Atsurou Yoshida, Yuji Higashi, Wataru Miyazaki, Teruhito Tanaka, Takashi Kambe (Kinki University)
(36) 16:10-16:35 New technology of independent-gate controlled Double-Gate transistor for system LSI VLD2007-168 ICD2007-191 Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.)
(37) 16:35-17:00 New design technology of independent-Gate controlled Stacked type 3D transistor for system LSI VLD2007-169 ICD2007-192 Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.)
(38) 17:00-17:25 Design of High Density LSI with Three-Dimensional Transistor FinFET
-- Effect of pattern Area Reduction with CMOS Cell Library --
VLD2007-170 ICD2007-193
Keisuke Okamoto, Keisuke Koizumi, Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.)

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Hiroyuki OCHI (Kyoto Univ.)
E-:oeek-u
Tel.075-753-4803 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
ICD Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
Contact Address Yoshio Hirose (Fujitsu Laboratories Ltd.)
TEL +81-44-754-2783, +81-44-754-2744
E-:y 


Last modified: 2008-02-27 13:59:11


Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 

[Presentation and Participation FAQ] (in Japanese)
 
[Cover and Index of IEICE Technical Report by Issue]
 

[Return to VLD Schedule Page]   /   [Return to ICD Schedule Page]   /  
 
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan