Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2008-03-07 15:45
A Circuit Design of Reed-Solomon Decoder using Dynamically Reconfigurable Processor
Atsurou Yoshida, Yuji Higashi, Wataru Miyazaki, Teruhito Tanaka, Takashi Kambe (Kinki University) VLD2007-167 ICD2007-190
Abstract (in Japanese) (See Japanese page) 
(in English) Reed-Solomon Decoder can correct continues error and it has been a popular technology for various
devices such as communication, hard disk, and DVD. This paper, proposes acceleration and reduction of circuit
scale of Reed-Solomon Decoder using ”Dynamically Reconfigurable Processor” and evaluates its performance.
Keyword (in Japanese) (See Japanese page) 
(in English) Reed-Solomon Decoder / Dynamically Reconfigurable Processor / DAPDNA-2 / Cycle based pipelining / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 508, VLD2007-167, pp. 65-68, March 2008.
Paper # VLD2007-167 
Date of Issue 2008-02-29 (VLD, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-167 ICD2007-190

Conference Information
Committee VLD ICD  
Conference Date 2008-03-05 - 2008-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English) TiRuRu 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System-on-silicon design techniques and related VLSs 
Paper Information
Registration To VLD 
Conference Code 2008-03-VLD-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Circuit Design of Reed-Solomon Decoder using Dynamically Reconfigurable Processor 
Sub Title (in English)  
Keyword(1) Reed-Solomon Decoder  
Keyword(2) Dynamically Reconfigurable Processor  
Keyword(3) DAPDNA-2  
Keyword(4) Cycle based pipelining  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Atsurou Yoshida  
1st Author's Affiliation Kinki University (Kinki University)
2nd Author's Name Yuji Higashi  
2nd Author's Affiliation Kinki University (Kinki University)
3rd Author's Name Wataru Miyazaki  
3rd Author's Affiliation Kinki University (Kinki University)
4th Author's Name Teruhito Tanaka  
4th Author's Affiliation Kinki University (Kinki University)
5th Author's Name Takashi Kambe  
5th Author's Affiliation Kinki University (Kinki University)
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2008-03-07 15:45:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2007-167, ICD2007-190 
Volume (vol) vol.107 
Number (no) no.508(VLD), no.511(ICD) 
Page pp.65-68 
#Pages 4 
Date of Issue 2008-02-29 (VLD, ICD) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan