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Paper Abstract and Keywords
Presentation 2008-03-14 15:25
Through-silicon Via Interconnection for 3D Integration Using Room-temperature Bonding
Naotaka Tanaka, Yasuhiro Yoshimura, Michihiro Kawashita (Hitachi), Toshihide Uematsu, Takahiro Naitoh, Takashi Akazawa (Renesas) SDM2007-277
Abstract (in Japanese) (See Japanese page) 
(in English) One approach to 3D technology is chip stacking using through-silicon vias (TSVs). Interconnects in a 3D assembly are potentially much shorter than in a 2D configuration, allowing for faster system speed and lower power consumption. However, it is extremely important to use cost-effective process technologies in practical use. Therefore, in our study, we propose a basic concept for interconnecting stacked chips with TSVs using a cost-effective process technology. The principal feature is to use a “mechanical-caulking” technique, which has been used widely in the mechanical-engineering field, enabling 3D interconnections between stacked chips. This makes it possible to interconnect them by only applying compressive force at room temperature. This paper presents the results obtained by using mechanical-caulking connections at room temperature accomplished by manufacturing a prototype of a chip-stacked package with TSV interconnections. A 3D-SiP composed of an existing MCU, an interposer, and an SDRAM chip with TSV interconnections was also manufactured.
Keyword (in Japanese) (See Japanese page) 
(in English) Through-silicon via / Mechanical caulking / Room temperature bonding / Dry etching / 3D interconnection / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 549, SDM2007-277, pp. 21-26, March 2008.
Paper # SDM2007-277 
Date of Issue 2008-03-07 (SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee SDM  
Conference Date 2008-03-14 - 2008-03-14 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SDM 
Conference Code 2008-03-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Through-silicon Via Interconnection for 3D Integration Using Room-temperature Bonding 
Sub Title (in English)  
Keyword(1) Through-silicon via  
Keyword(2) Mechanical caulking  
Keyword(3) Room temperature bonding  
Keyword(4) Dry etching  
Keyword(5) 3D interconnection  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Naotaka Tanaka  
1st Author's Affiliation Hitachi (Hitachi)
2nd Author's Name Yasuhiro Yoshimura  
2nd Author's Affiliation Hitachi (Hitachi)
3rd Author's Name Michihiro Kawashita  
3rd Author's Affiliation Hitachi (Hitachi)
4th Author's Name Toshihide Uematsu  
4th Author's Affiliation Renesas Technology Corporation (Renesas)
5th Author's Name Takahiro Naitoh  
5th Author's Affiliation Renesas Technology Corporation (Renesas)
6th Author's Name Takashi Akazawa  
6th Author's Affiliation Renesas Technology Corporation (Renesas)
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Speaker Author-1 
Date Time 2008-03-14 15:25:00 
Presentation Time 25 minutes 
Registration for SDM 
Paper # SDM2007-277 
Volume (vol) vol.107 
Number (no) no.549 
Page pp.21-26 
#Pages 6 
Date of Issue 2008-03-07 (SDM) 

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