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Paper Abstract and Keywords
Presentation 2008-04-17 10:15
[Invited Talk] 65nm Low-Power High-Density SRAM Operable at 1.0V under 3sigma Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS
Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda, Yasuhisa Shimazaki (Renesas), Kenichi Osada (Hitachi, Ltd.) ICD2008-2
Abstract (in Japanese) (See Japanese page) 
(in English) A 1Mb SRAM is fabricated in 65nm LP process with 0.51μm2 cell. An NMOS and PMOS separately applied body bias technique and NMOS and PMOS individual Vth measurement method using leakage control are implemented to the prototype chip, which achieves 1.0-V operation under 3-σ systematic Vth variation.
Keyword (in Japanese) (See Japanese page) 
(in English) low-power SRAM / body bias / Vth measurement / / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 6, ICD2008-2, pp. 7-12, April 2008.
Paper # ICD2008-2 
Date of Issue 2008-04-10 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ICD  
Conference Date 2008-04-17 - 2008-04-18 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2008-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) 65nm Low-Power High-Density SRAM Operable at 1.0V under 3sigma Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS 
Sub Title (in English)  
Keyword(1) low-power SRAM  
Keyword(2) body bias  
Keyword(3) Vth measurement  
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1st Author's Name Masanao Yamaoka  
1st Author's Affiliation Hitachi, Ltd. (Hitachi, Ltd.)
2nd Author's Name Noriaki Maeda  
2nd Author's Affiliation Renesas Technology Corp. (Renesas)
3rd Author's Name Yasuhisa Shimazaki  
3rd Author's Affiliation Renesas Technology Corp. (Renesas)
4th Author's Name Kenichi Osada  
4th Author's Affiliation Hitachi, Ltd. (Hitachi, Ltd.)
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Speaker Author-1 
Date Time 2008-04-17 10:15:00 
Presentation Time 50 minutes 
Registration for ICD 
Paper # ICD2008-2 
Volume (vol) vol.108 
Number (no) no.6 
Page pp.7-12 
#Pages 6 
Date of Issue 2008-04-10 (ICD) 

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