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Paper Abstract and Keywords
Presentation 2008-04-18 13:55
A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme
Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Hiroaki Honjo, Shinsaku Saito, Yuko Kato, Naoki Kasai (NEC) ICD2008-12
Abstract (in Japanese) (See Japanese page) 
(in English) We propose an MRAM macro architecture for SoCs to reduce their area size. The shared write-selection transistor (SWST) architecture is based on 2T1MTJ MRAM cell technology, which enables the same fast access time as and with smaller cell area than as that of 6T SRAMs. We designed a 4Mb macro using the SWST architecture with a 0.15μm CMOS process and a 0.24μm MRAM process. The macro cell array consists of 81T64MTJ cell array elements, each storing 64bits of data. Area size is reduced by 30%, and by introducing a leakage-replication (LR) read scheme, 50ns access time is achieved with SPICE simulation. The 2T1MTJ macro and 81T64MTJ macro can be integrated into a single SoC.
Keyword (in Japanese) (See Japanese page) 
(in English) MRAM / Embedded Memories / SoC / / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 6, ICD2008-12, pp. 63-68, April 2008.
Paper # ICD2008-12 
Date of Issue 2008-04-10 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ICD  
Conference Date 2008-04-17 - 2008-04-18 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2008-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme 
Sub Title (in English)  
Keyword(1) MRAM  
Keyword(2) Embedded Memories  
Keyword(3) SoC  
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1st Author's Name Ryusuke Nebashi  
1st Author's Affiliation NEC Corporation (NEC)
2nd Author's Name Noboru Sakimura  
2nd Author's Affiliation NEC Corporation (NEC)
3rd Author's Name Tadahiko Sugibayashi  
3rd Author's Affiliation NEC Corporation (NEC)
4th Author's Name Hiroaki Honjo  
4th Author's Affiliation NEC Corporation (NEC)
5th Author's Name Shinsaku Saito  
5th Author's Affiliation NEC Corporation (NEC)
6th Author's Name Yuko Kato  
6th Author's Affiliation NEC Corporation (NEC)
7th Author's Name Naoki Kasai  
7th Author's Affiliation NEC Corporation (NEC)
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Speaker Author-1 
Date Time 2008-04-18 13:55:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2008-12 
Volume (vol) vol.108 
Number (no) no.6 
Page pp.63-68 
#Pages 6 
Date of Issue 2008-04-10 (ICD) 

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