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| Paper Abstract and Keywords | ||
| Presentation | 2008-04-23 15:30 Influence of Untestable Hard Error on Soft Error Hardened Latches Kengo Nakashima, Kazuteru Namba, Hideo Ito (Chiba Univ)  CPSY2008-8 DC2008-8 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In recent high-density, high-speed and low-power VLSIs, soft errors frequently occur, and soft error hardened design becomes essential. Soft error hardened latches were proposed as one of techniques correcting soft errors occurring on latches in VLSI systems. Some manufacturing faults occurring on the soft error hardened latches are untestable. Even if such faults occur, the latches work correctly as long as no soft errors occur. However, the faulty latches may have only lower soft error correcting capability than fault-free latches. This paper provides an analysis of soft error correcting capability of soft error hardened latches that untestable manufacturing open and short faults occur. On soft error hardened latches that open and short fault occur, uncorrectable soft errors occur 8.663×10-17and 9.789×10-17times per an hour, respectively. The probability that uncorrectable soft errors occur on faulty circuits with soft error hardened latches is 10-4～10-5 times lower than one that soft errors occur on fault-free circuits without soft error hardened latches. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Soft Error / Latch / Soft Error Rate / Open Fault / Short Fault / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 15, DC2008-8, pp. 43-48, April 2008. | |
| Paper # | DC2008-8 | |
| Date of Issue | 2008-04-16 (CPSY, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2008-8 DC2008-8 |
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| Conference Information | |
| Committee | DC CPSY |
| Conference Date | 2008-04-23 - 2008-04-23 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Tokyo Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Dependable Computing Systems, etc. |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2008-04-DC-CPSY |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Influence of Untestable Hard Error on Soft Error Hardened Latches |
| Sub Title (in English) | |
| Keyword(1) | Soft Error |
| Keyword(2) | Latch |
| Keyword(3) | Soft Error Rate |
| Keyword(4) | Open Fault |
| Keyword(5) | Short Fault |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kengo Nakashima |
| 1st Author's Affiliation | Chiba University (Chiba Univ) |
| 2nd Author's Name | Kazuteru Namba |
| 2nd Author's Affiliation | Chiba University (Chiba Univ) |
| 3rd Author's Name | Hideo Ito |
| 3rd Author's Affiliation | Chiba University (Chiba Univ) |
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| Speaker | Author-1 |
| Date Time | 2008-04-23 15:30:00 |
| Presentation Time | 30 minutes |
| Registration for | DC |
| Paper # | CPSY2008-8, DC2008-8 |
| Volume (vol) | vol.108 |
| Number (no) | no.14(CPSY), no.15(DC) |
| Page | pp.43-48 |
| #Pages | 6 |
| Date of Issue | 2008-04-16 (CPSY, DC) |
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