Paper Abstract and Keywords |
Presentation |
2008-05-08 14:45
Checker Circuit Generation for System Verilog Assertions in Prototyping Verification Mengru Wang, Shinji Kimura (Waseda Univ.) VLD2008-2 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Reduction of verification period is the crucial problem in the recent LSI designs, and prototyping/emulation technologies are used for the reduction. Assertion-Based Verification (ABV) has been paid attention to check design errors at run time in simulation, and it has become an important to combine ABV with the prototyping. In the manuscript, we discuss about a generation method of checker circuit for SystemVerilog Assertions (SVA's). SVA is one of standard method to describe assertions in ABV. In the checker circuit generation, we focus on the hardware cost reduction. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Assertion-Based Verification / SystemVerilog Assertion / / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 108, no. 22, VLD2008-2, pp. 7-12, May 2008. |
Paper # |
VLD2008-2 |
Date of Issue |
2008-05-01 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2008-2 |
Conference Information |
Committee |
VLD IPSJ-SLDM |
Conference Date |
2008-05-08 - 2008-05-09 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kobe Univ. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
System Design, etc. |
Paper Information |
Registration To |
VLD |
Conference Code |
2008-05-VLD-SLDM |
Language |
English (Japanese title is available) |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Checker Circuit Generation for System Verilog Assertions in Prototyping Verification |
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Assertion-Based Verification |
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SystemVerilog Assertion |
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1st Author's Name |
Mengru Wang |
1st Author's Affiliation |
Waseda University (Waseda Univ.) |
2nd Author's Name |
Shinji Kimura |
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Waseda University (Waseda Univ.) |
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Speaker |
Author-1 |
Date Time |
2008-05-08 14:45:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2008-2 |
Volume (vol) |
vol.108 |
Number (no) |
no.22 |
Page |
pp.7-12 |
#Pages |
6 |
Date of Issue |
2008-05-01 (VLD) |
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