| （英） |
We propose a novel dependable SRAM with 7T memory cell pair, and introduce a new concept, “quality of a bit （QoB）” for it. The proposed SRAM has three modes: a typical mode, high-speed mode, and dependable mode, in which the QoB is scalable. That is, the area, speed, reliability, and/or power of one-bit information can be controlled. In the typical mode, assignment of information is as usual as one memory cell has one bit. On the other hand, in the high-speed or dependable mode, one-bit information is stored in two memory cells, which boosts the speed or increases the reliability. In the high speed mode, the cell current is increased by 142%, and bitline discharge time is reduced by 66.3%. Furthermore, in dependable mode, Bit error rate （BER） in proposed SRAM is improved by 2.510-2. Compared with the conventional 6T memory cell, the respective area overheads are 30% and 12%, in the nMOS and pMOS additional cases. |