| Paper Abstract and Keywords |
| Presentation |
2008-05-09 14:35
A Dependable SRAM with high-reliability mode and high-speed mode.
Shunsuke Okumura, Hidehiro Fujiwara, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
We propose a novel dependable SRAM with 7T memory cell pair, and introduce a new concept, “quality of a bit （QoB）” for it. The proposed SRAM has three modes: a typical mode, high-speed mode, and dependable mode, in which the QoB is scalable. That is, the area, speed, reliability, and/or power of one-bit information can be controlled. In the typical mode, assignment of information is as usual as one memory cell has one bit. On the other hand, in the high-speed or dependable mode, one-bit information is stored in two memory cells, which boosts the speed or increases the reliability. In the high speed mode, the cell current is increased by 142%, and bitline discharge time is reduced by 66.3%. Furthermore, in dependable mode, Bit error rate （BER） in proposed SRAM is improved by 2.510-2. Compared with the conventional 6T memory cell, the respective area overheads are 30% and 12%, in the nMOS and pMOS additional cases. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
SRAM / Dependable LSI / Quality of a bit / / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 108, pp. 31-36, May 2008. |
| Paper # |
|
| Date of Issue |
2008-05-02 (VLD) |
| ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
| Download PDF |
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| Conference Information |
| Committee |
VLD IPSJ-SLDM |
| Conference Date |
2008-05-08 - 2008-05-09 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Kobe Univ. |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
System Design, etc. |
| Paper Information |
| Registration To |
IPSJ-SLDM |
| Conference Code |
2008-05-VLD-SLDM |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
A Dependable SRAM with high-reliability mode and high-speed mode. |
| Sub Title (in English) |
|
| Keyword(1) |
SRAM |
| Keyword(2) |
Dependable LSI |
| Keyword(3) |
Quality of a bit |
| Keyword(4) |
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| 1st Author's Name |
Shunsuke Okumura |
| 1st Author's Affiliation |
Kobe University (Kobe Univ.) |
| 2nd Author's Name |
Hidehiro Fujiwara |
| 2nd Author's Affiliation |
Kobe University (Kobe Univ.) |
| 3rd Author's Name |
Yusuke Iguchi |
| 3rd Author's Affiliation |
Kobe University (Kobe Univ.) |
| 4th Author's Name |
Hiroki Noguchi |
| 4th Author's Affiliation |
Kobe University (Kobe Univ.) |
| 5th Author's Name |
Yasuhiro Morita |
| 5th Author's Affiliation |
Kobe University (Kobe Univ.) |
| 6th Author's Name |
Hiroshi Kawaguchi |
| 6th Author's Affiliation |
Kobe University (Kobe Univ.) |
| 7th Author's Name |
Masahiko Yoshimoto |
| 7th Author's Affiliation |
Kobe University (Kobe Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2008-05-09 14:35:00 |
| Presentation Time |
25 minutes |
| Registration for |
IPSJ-SLDM |
| Paper # |
VLD2008-12 |
| Volume (vol) |
vol.108 |
| Number (no) |
no.23 |
| Page |
pp.31-36 |
| #Pages |
6 |
| Date of Issue |
2008-05-02 (VLD) |