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Paper Abstract and Keywords
Presentation 2008-06-12 14:25
VLSI Architecture of a Pipelined MMSE Detector in a 4x4 MIMO-OFDM Receiver
Shingo Yoshizawa, Yoshikazu Miyanaga (Hokkaido Univ.) SIS2008-9
Abstract (in Japanese) (See Japanese page) 
(in English) This report presents a VLSI architecture of MMSE detection in a 4x4 MIMO-OFDM receiver. Packet-based MIMO-OFDM imposes a considerable throughput requirement on the matrix inversion because of strict timing in frame structure and subcarrier-by-subcarrier basis processing. Pipeline processing oriented algorithms are preferable to tackle this issue. We propose a pipelined MMSE detector using Strassen's algorithms of matrix inversion and multiplication. This circuit achieves real-time operation which does not depend on numbers of subcarriers. The designed circuit has been implemented to a 90-nm CMOS process and evaluated in processing latency, circuit area, and power consumption.
Keyword (in Japanese) (See Japanese page) 
(in English) MIMO-OFDM / MIMO Decoder / MMSE Detection / VLSI Architecture / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 85, SIS2008-9, pp. 47-52, June 2008.
Paper # SIS2008-9 
Date of Issue 2008-06-05 (SIS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SIS2008-9

Conference Information
Committee SIS  
Conference Date 2008-06-12 - 2008-06-13 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SIS 
Conference Code 2008-06-SIS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) VLSI Architecture of a Pipelined MMSE Detector in a 4x4 MIMO-OFDM Receiver 
Sub Title (in English)  
Keyword(1) MIMO-OFDM  
Keyword(2) MIMO Decoder  
Keyword(3) MMSE Detection  
Keyword(4) VLSI Architecture  
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1st Author's Name Shingo Yoshizawa  
1st Author's Affiliation Hokkaido University (Hokkaido Univ.)
2nd Author's Name Yoshikazu Miyanaga  
2nd Author's Affiliation Hokkaido University (Hokkaido Univ.)
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Speaker Author-1 
Date Time 2008-06-12 14:25:00 
Presentation Time 25 minutes 
Registration for SIS 
Paper # SIS2008-9 
Volume (vol) vol.108 
Number (no) no.85 
Page pp.47-52 
#Pages 6 
Date of Issue 2008-06-05 (SIS) 

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