| Paper Abstract and Keywords |
| Presentation |
2008-07-10 10:55
Scalability of Vertical MOSFETs in Sub-10nm generation and its Mechanism Yuto Norifusa, Tetsuo Endoh (Tohoku Univ.) ED2008-60 SDM2008-79 |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
In this paper, the device performances of sub-10nm Vertical MOSFETs are investigated. One of the drawbacks of conventional planar MOSFETs is that in the sub-10nm generation, its cutoff leakage current increases due to the short channel effects, but even more, its driving current decreases due to the quantum mechanical confinement effects such as the sub-band effect and the depletion of the inversion layer. It is shown for the first time that by downscaling the silicon pillar diameter from 20nm to 4nm, the Vertical MOSFET increases its driving current per footprint to about 2 times and suppresses its total cutoff leakage current per footprint to less than 1/60 at the same time. Moreover, the mechanisms of these improvements of Vertical MOSFET performances are clarified. The results of this work show that Vertical MOSFETs can overcome the drawbacks of conventional planar MOSFETs and achieve the high device performance through the sub-10nm generation. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Vertical MOSFET / sub-10nm / driving current / cutoff leakage current / current density / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 108, no. 122, SDM2008-79, pp. 107-111, July 2008. |
| Paper # |
SDM2008-79 |
| Date of Issue |
2008-07-02 (ED, SDM) |
| ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Download PDF |
ED2008-60 SDM2008-79 |
| Conference Information |
| Committee |
SDM ED |
| Conference Date |
2008-07-09 - 2008-07-11 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Kaderu2・7 |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
2008 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices |
| Paper Information |
| Registration To |
SDM |
| Conference Code |
2008-07-SDM-ED |
| Language |
English |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Scalability of Vertical MOSFETs in Sub-10nm generation and its Mechanism |
| Sub Title (in English) |
|
| Keyword(1) |
Vertical MOSFET |
| Keyword(2) |
sub-10nm |
| Keyword(3) |
driving current |
| Keyword(4) |
cutoff leakage current |
| Keyword(5) |
current density |
| Keyword(6) |
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| Keyword(7) |
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| Keyword(8) |
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| 1st Author's Name |
Yuto Norifusa |
| 1st Author's Affiliation |
Tohoku University (Tohoku Univ.) |
| 2nd Author's Name |
Tetsuo Endoh |
| 2nd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2008-07-10 10:55:00 |
| Presentation Time |
15 minutes |
| Registration for |
SDM |
| Paper # |
ED2008-60, SDM2008-79 |
| Volume (vol) |
vol.108 |
| Number (no) |
no.121(ED), no.122(SDM) |
| Page |
pp.107-111 |
| #Pages |
5 |
| Date of Issue |
2008-07-02 (ED, SDM) |