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Paper Abstract and Keywords
Presentation 2008-07-17 15:05
A Fully Logic-Process-Compatible, SESO-memory Cell with 0.1-FIT/Mb Soft Error, 100-MHz Random Cycle, and 100-ms Retention
Norifumi Kameshiro, Takao Watanabe, Tomoyuki Ishii, Toshiyuki Mine (Hitachi, Ltd.), Toshiaki Sano (Renesas), Hidefumi Ibe, Satoru Akiyama (Hitachi, Ltd.), Kazumasa Yanagisawa, Takashi Ipposhi, Toshiaki Iwamatsu, Yasuhiko Takahashi (Renesas) SDM2008-136 ICD2008-46
Abstract (in Japanese) (See Japanese page) 
(in English) We proposed a fully logic compatible process for a single electron shut-off transistor (SESO). A 1-kb memory-cell array composed of SESO cells was fabricated with the 90-nm logic process for the first time. It features a 0.1-FIT/Mb soft error, 100-MHz random cycle, and 100-ms retention. In addition to a logic-compatible cell structure and a write-data caching scheme, a backup latch circuit with SESO transistors for logic application was also fabricated.
Keyword (in Japanese) (See Japanese page) 
(in English) Embedded memory / 3TR Cell / TFT / Low leakage current / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 140, ICD2008-46, pp. 47-52, July 2008.
Paper # ICD2008-46 
Date of Issue 2008-07-10 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2008-136 ICD2008-46

Conference Information
Committee ICD SDM  
Conference Date 2008-07-17 - 2008-07-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2008-07-ICD-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Fully Logic-Process-Compatible, SESO-memory Cell with 0.1-FIT/Mb Soft Error, 100-MHz Random Cycle, and 100-ms Retention 
Sub Title (in English)  
Keyword(1) Embedded memory  
Keyword(2) 3TR Cell  
Keyword(3) TFT  
Keyword(4) Low leakage current  
Keyword(5)  
Keyword(6)  
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1st Author's Name Norifumi Kameshiro  
1st Author's Affiliation Central Research Lav. Hitachi, LTd. (Hitachi, Ltd.)
2nd Author's Name Takao Watanabe  
2nd Author's Affiliation Central Research Lav. Hitachi, LTd. (Hitachi, Ltd.)
3rd Author's Name Tomoyuki Ishii  
3rd Author's Affiliation Central Research Lav. Hitachi, LTd. (Hitachi, Ltd.)
4th Author's Name Toshiyuki Mine  
4th Author's Affiliation Central Research Lav. Hitachi, LTd. (Hitachi, Ltd.)
5th Author's Name Toshiaki Sano  
5th Author's Affiliation Renesas Northern Japan Semiconductor, Inc. (Renesas)
6th Author's Name Hidefumi Ibe  
6th Author's Affiliation Production EEngineering Research Lab. Hitachi, Ltd. (Hitachi, Ltd.)
7th Author's Name Satoru Akiyama  
7th Author's Affiliation Production EEngineering Research Lab. Hitachi, Ltd. (Hitachi, Ltd.)
8th Author's Name Kazumasa Yanagisawa  
8th Author's Affiliation Renesas Technology Corp. (Renesas)
9th Author's Name Takashi Ipposhi  
9th Author's Affiliation Renesas Technology Corp. (Renesas)
10th Author's Name Toshiaki Iwamatsu  
10th Author's Affiliation Renesas Technology Corp. (Renesas)
11th Author's Name Yasuhiko Takahashi  
11th Author's Affiliation Renesas Technology Corp. (Renesas)
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Speaker Author-1 
Date Time 2008-07-17 15:05:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # SDM2008-136, ICD2008-46 
Volume (vol) vol.108 
Number (no) no.139(SDM), no.140(ICD) 
Page pp.47-52 
#Pages 6 
Date of Issue 2008-07-10 (SDM, ICD) 

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