Paper Abstract and Keywords |
Presentation |
2008-07-17 10:30
A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka (Renesas Tech.), Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Katsuji Satomi, Hironori Akamatsu (Matsushita Elec.), Hirofumi Shinohara (Renesas Tech.) SDM2008-131 ICD2008-41 Link to ES Tech. Rep. Archives: SDM2008-131 ICD2008-41 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We develop 512 Kb SRAM module in 45 nm LSTP CMOS technology with the variation tolerant assist circuits against process and temperature. We introduce a passive resistance to the read assist circuit, and adopt the divided VDD line in the memory cell array to the write assist circuit. The SRAM cell areas with 0.245 μm2 and 0.327μm2 are fabricated. From the measurements, we show that, by using our circuitry, the SNM exceeds 120 mV and the write margin is improved by 15% in the worst PVT condition. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
SRAM / Assist circuit / 45nm CMOS / Variability / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 108, no. 140, ICD2008-41, pp. 17-22, July 2008. |
Paper # |
ICD2008-41 |
Date of Issue |
2008-07-10 (SDM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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SDM2008-131 ICD2008-41 Link to ES Tech. Rep. Archives: SDM2008-131 ICD2008-41 |
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