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Paper Abstract and Keywords
Presentation 2008-09-12 17:00
How to introduce the dynamic key to a provably Secure Block Cipher using FPGA Partial Reconfiguration
Kenji Takahashi, Tetsuya Ichikawa (Mitsubishi Electric Engineering), Toru Sorimachi (Mitsubishi Electric) ISEC2008-72
Abstract (in Japanese) (See Japanese page) 
(in English) Cipher circuits are required both to have high security and to show high performance as to circuit scale and processing speed. One way to improve security is to implement various algorithms or many variations of an algorithm on a circuit. In this case, however, the security is achieved at the cost of the performance, that is, the circuit becomes so large that security and performance do not meet.
We therefore employ FPGA partial reconfiguration technique and apply dynamic key methods to provably secure block ciphers in order to achieve both security and performance. We choose the 64 bit block cipher MISTY1, realize the dynamic key modification to it in two ways, the partial reconfiguration one and the usual one using selectors, and compare the results. The study finds that it is effective to use the partial reconfiguration when there are four or more circuits to be selected.
Keyword (in Japanese) (See Japanese page) 
(in English) Block Cipher / Dynamic Key / Implementation / FPGA / Partial Reconfiguration / Run-time Reconfiguration / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 207, ISEC2008-72, pp. 63-68, Sept. 2008.
Paper # ISEC2008-72 
Date of Issue 2008-09-05 (ISEC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ISEC  
Conference Date 2008-09-12 - 2008-09-12 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ISEC 
Conference Code 2008-09-ISEC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) How to introduce the dynamic key to a provably Secure Block Cipher using FPGA Partial Reconfiguration 
Sub Title (in English)  
Keyword(1) Block Cipher  
Keyword(2) Dynamic Key  
Keyword(3) Implementation  
Keyword(4) FPGA  
Keyword(5) Partial Reconfiguration  
Keyword(6) Run-time Reconfiguration  
Keyword(7)  
Keyword(8)  
1st Author's Name Kenji Takahashi  
1st Author's Affiliation Mitsubishi Electric Engineering Company Limited (Mitsubishi Electric Engineering)
2nd Author's Name Tetsuya Ichikawa  
2nd Author's Affiliation Mitsubishi Electric Engineering Company Limited (Mitsubishi Electric Engineering)
3rd Author's Name Toru Sorimachi  
3rd Author's Affiliation Mitsubishi Electric Corporation (Mitsubishi Electric)
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Speaker Author-1 
Date Time 2008-09-12 17:00:00 
Presentation Time 25 minutes 
Registration for ISEC 
Paper # ISEC2008-72 
Volume (vol) vol.108 
Number (no) no.207 
Page pp.63-68 
#Pages 6 
Date of Issue 2008-09-05 (ISEC) 

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