Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2008-09-29 16:40
Design and Evalution of a Butterfly Circuit Using Selector Logic by Bit-Level Transformation
Takeshi Namura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Motonobu Tonomura (Dai Nippon Print) VLD2008-52
Abstract (in Japanese) (See Japanese page) 
(in English) An arithmetic circuit using selector logic has been proposed,
as a high computational approach for processing.
In this paper, we propose a radix-2 butterfly circuit architecture using selector logic by bit-level taransformation for high computational requirement of FFT. Our butterfly circuit reduces carry propagations, compared to conventional butterfly circuits.
Experimental results show that our proposed butterfly circuit improves the performance by 37.1% to 49.8% with no area overhead, compared to conventional butterfly circuits under area constraint design.
Keyword (in Japanese) (See Japanese page) 
(in English) selector logic / bit-level transformation / butterfly circuit / FFT / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 224, VLD2008-52, pp. 31-36, Sept. 2008.
Paper # VLD2008-52 
Date of Issue 2008-09-22 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2008-52

Conference Information
Committee VLD  
Conference Date 2008-09-29 - 2008-09-30 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Physical Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2008-09-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design and Evalution of a Butterfly Circuit Using Selector Logic by Bit-Level Transformation 
Sub Title (in English)  
Keyword(1) selector logic  
Keyword(2) bit-level transformation  
Keyword(3) butterfly circuit  
Keyword(4) FFT  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Takeshi Namura  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Nozomu Togawa  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Masao Yanagisawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name Tatsuo Ohtsuki  
4th Author's Affiliation Waseda University (Waseda Univ.)
5th Author's Name Motonobu Tonomura  
5th Author's Affiliation Dai Nippon Printing Corporation (Dai Nippon Print)
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2008-09-29 16:40:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2008-52 
Volume (vol) vol.108 
Number (no) no.224 
Page pp.31-36 
#Pages 6 
Date of Issue 2008-09-22 (VLD) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan