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Paper Abstract and Keywords
Presentation 2008-09-29 16:15
Delay Variation-Aware Datapath Synthesis Based on Register Clustering
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST) VLD2008-51
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, a novel delay variation-tolerant datapath class named structural robustness against delay variation (SRV) has been proposed by the authors. Its major drawback is the increase in the number of registers, which causes area overhead and extra power consumption. Therefore we have to minimize the number of registers. In this paper, we introduce the concept ``cluster'' (a subset of registers). Registers in a cluster are to be closely placed, and the relative difference of the arrival time of the control signals for registers in a cluster is assumed to be negligibly small. The number of registers which is needed for SRV-based register
assignment can be decreased by this clustering technique. We formulate the simultaneous register assignment and clustering problem in datapath synthesis. If the available cluster size is equal to 1, the problem is reduced to the original SRV-based register assignment, and if the cluster size is more than or equal to the maximum number of data-lifetime overlaps, the problem is reduced to the conventional register assignment.
Both of the problems can be solved in a polynomial time. In general, the problem is NP-hard, and we derive an integer linear programming (ILP) formulation.
Keyword (in Japanese) (See Japanese page) 
(in English) Register clustering / datapath synthesis / register assignment / delay variation / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 224, VLD2008-51, pp. 25-30, Sept. 2008.
Paper # VLD2008-51 
Date of Issue 2008-09-22 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee VLD  
Conference Date 2008-09-29 - 2008-09-30 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Physical Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2008-09-VLD 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Delay Variation-Aware Datapath Synthesis Based on Register Clustering 
Sub Title (in English)  
Keyword(1) Register clustering  
Keyword(2) datapath synthesis  
Keyword(3) register assignment  
Keyword(4) delay variation  
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1st Author's Name Keisuke Inoue  
1st Author's Affiliation Japan Advanced Institute of Science and Technology (JAIST)
2nd Author's Name Mineo Kaneko  
2nd Author's Affiliation Japan Advanced Institute of Science and Technology (JAIST)
3rd Author's Name Tsuyoshi Iwagaki  
3rd Author's Affiliation Japan Advanced Institute of Science and Technology (JAIST)
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Speaker Author-1 
Date Time 2008-09-29 16:15:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2008-51 
Volume (vol) vol.108 
Number (no) no.224 
Page pp.25-30 
#Pages 6 
Date of Issue 2008-09-22 (VLD) 

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