講演抄録/キーワード |
講演名 |
2008-10-20 13:55
An implementation of a fault-tolerant 2D systolic array on an FPGA and its evaluation ○Tadayoshi Horita(Polytechnic Univ.)・Itsuo Takanami(Ichinoseki National College of Tech. in former times) DC2008-23 |
抄録 |
(和) |
(まだ登録されていません) |
(英) |
A fault-tolerant self-reconfigurable 2D systolic array to calculate matrix multiplications is implemented on an FPGA.
The array uses a 1.5-track switching network for reconfiguration.
The array implemented is compared with the corresponding non-redundant case
by simulations for concrete examples,
in terms of hardware size, total array reliability considering not only faults of processing elements but also faults in the switching networks,
fabrication-time cost and computation time.
Then it is shown that the fault-tolerant array is better than the the corresponding non-redundant one,
in terms of fabrication-time cost and the total array reliability,
even if faults of switching networks are not negligible,
by giving the concrete data.
This must be useful for designing fault-tolerant 2D arrays. |
キーワード |
(和) |
/ / / / / / / |
(英) |
systolic array / 1.5-track switches / FPGA / run-time fault-tolerance / self-reconfiguration / / / |
文献情報 |
信学技報, vol. 108, no. 248, DC2008-23, pp. 7-12, 2008年10月. |
資料番号 |
DC2008-23 |
発行日 |
2008-10-13 (DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
DC2008-23 |