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Paper Abstract and Keywords
Presentation 2008-10-20 13:55
An implementation of a fault-tolerant 2D systolic array on an FPGA and its evaluation
Tadayoshi Horita (Polytechnic Univ.), Itsuo Takanami (Ichinoseki National College of Tech. in former times) DC2008-23
Abstract (in Japanese) (See Japanese page) 
(in English) A fault-tolerant self-reconfigurable 2D systolic array to calculate matrix multiplications is implemented on an FPGA.
The array uses a 1.5-track switching network for reconfiguration.
The array implemented is compared with the corresponding non-redundant case
by simulations for concrete examples,
in terms of hardware size, total array reliability considering not only faults of processing elements but also faults in the switching networks,
fabrication-time cost and computation time.
Then it is shown that the fault-tolerant array is better than the the corresponding non-redundant one,
in terms of fabrication-time cost and the total array reliability,
even if faults of switching networks are not negligible,
by giving the concrete data.
This must be useful for designing fault-tolerant 2D arrays.
Keyword (in Japanese) (See Japanese page) 
(in English) systolic array / 1.5-track switches / FPGA / run-time fault-tolerance / self-reconfiguration / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 248, DC2008-23, pp. 7-12, Oct. 2008.
Paper # DC2008-23 
Date of Issue 2008-10-13 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2008-10-20 - 2008-10-20 
Place (in Japanese) (See Japanese page) 
Place (in English) National Center of Sciences 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2008-10-DC 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An implementation of a fault-tolerant 2D systolic array on an FPGA and its evaluation 
Sub Title (in English)  
Keyword(1) systolic array  
Keyword(2) 1.5-track switches  
Keyword(3) FPGA  
Keyword(4) run-time fault-tolerance  
Keyword(5) self-reconfiguration  
1st Author's Name Tadayoshi Horita  
1st Author's Affiliation Polytechnic University (Polytechnic Univ.)
2nd Author's Name Itsuo Takanami  
2nd Author's Affiliation Ichinoseki National College of Technology in former times (Ichinoseki National College of Tech. in former times)
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Speaker Author-1 
Date Time 2008-10-20 13:55:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2008-23 
Volume (vol) vol.108 
Number (no) no.248 
Page pp.7-12 
Date of Issue 2008-10-13 (DC) 

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