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Paper Abstract and Keywords
Presentation 2008-10-23 14:10
[Invited Talk] Analog design isuues of high-resolution and low-power ADCs using a low voltage supply and sub-micron proceses
Kunihiko Gotoh (FUJITSU LABORATORIES LTD.) ICD2008-76
Abstract (in Japanese) (See Japanese page) 
(in English) The demand for high-speed (≧30 MS/s), high-resolution (≧10 bit) and low-power operation analog-to-digital converters (ADC) is increasing because of the rapid growth in digital consumer applications (e.g., DTV and DSC) and wireless communications. Recently, the hardware in these applications has been developed with system on a chip (SoC) devices that incorporate deep sub-micron CMOS processes. Furthermore, an accurate operation at a low supply (under 1.2 V) is also required of these devices. But. it is a challenging task to design a high-accuracy and low-power ADC to operate under 1.2-V supply, because of the reduction of the input signal range. In the case of a low input signal range, the sampling capacitor value and the analog current of the op-amp used in the ADC must be increased because the thermal noise (kT/C) must be reduced to correspond with the scaling-down of the input signal power. This means that the analog power consumption and die size of the ADC increases in spite of using a low supply voltage and a deep sub-micron CMOS process.
This paper describes analog design issues using a low voltage supply and a deep sub-micron process for a pipelined ADC, and introduces some new approaches on solving these problems with the pipelined ADC.
Keyword (in Japanese) (See Japanese page) 
(in English) sub-micron CMOS process / pipeline ADC / amplifier / low-voltage / low-noise / low-power / low-cost /  
Reference Info. IEICE Tech. Rep., vol. 108, pp. 101-106, Oct. 2008.
Paper #  
Date of Issue 2008-10-15 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2008-76

Conference Information
Committee ICD ITE-IST  
Conference Date 2008-10-22 - 2008-10-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Hokkaido University 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ITE-IST 
Conference Code 2008-10-ICD-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Analog design isuues of high-resolution and low-power ADCs using a low voltage supply and sub-micron proceses 
Sub Title (in English)  
Keyword(1) sub-micron CMOS process  
Keyword(2) pipeline ADC  
Keyword(3) amplifier  
Keyword(4) low-voltage  
Keyword(5) low-noise  
Keyword(6) low-power  
Keyword(7) low-cost  
Keyword(8)  
1st Author's Name Kunihiko Gotoh  
1st Author's Affiliation FUJITSU LABORATORIES LIMITED (FUJITSU LABORATORIES LTD.)
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Speaker Author-1 
Date Time 2008-10-23 14:10:00 
Presentation Time 50 minutes 
Registration for ITE-IST 
Paper # ICD2008-76 
Volume (vol) vol.108 
Number (no) no.253 
Page pp.101-106 
#Pages 6 
Date of Issue 2008-10-15 (ICD) 

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