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Paper Abstract and Keywords
Presentation 2008-10-31 11:15
[Special Invited Talk] The Proposal of the MPLD Architecture for High Performance Computing
Tetsuo Hironaka, Naoki Hirakawa (Hiroshima City Univ.), Masanori Yoshihara (Hiroshima City Univ./Renesas Technorogy Corp.), Kazuya Tanigawa (Hiroshima City Univ.), Masayuki Sato (Taiyo Yuden Co., Ltd.) CPSY2008-31
Abstract (in Japanese) (See Japanese page) 
(in English) As the practical use of high performance FPGA increases, research on using FPGAs in the field of HPC (High Performance Computing) for scientific calculation is recently increasing. In contrast to the high-speed operation frequency of CPU, the configuration speed of FPGA is quite slow, which cause a serious overhead by the difference of CPU processing time and FPGA configuration time on HPC. Also in general, arithmetic operations in the FPGA and data in memory are separated by external I/Os which arises overhead for executing highly parallel operation in the FPGA.
To avoid the overheads, we present a FPGA which can be partially reconfigured by the same action used for writing data in a memory, and also present the possibility for an FPGA for accessing memory without using external I/Os for reading and writing results of arithmetic operation done in the FPGA.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA architecture / configuration / partial configuration / / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 273, CPSY2008-31, pp. 13-18, Oct. 2008.
Paper # CPSY2008-31 
Date of Issue 2008-10-24 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee CPSY  
Conference Date 2008-10-31 - 2008-10-31 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiroshima City Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Advanced Computer System Technologies, etc. 
Paper Information
Registration To CPSY 
Conference Code 2008-10-CPSY 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) The Proposal of the MPLD Architecture for High Performance Computing 
Sub Title (in English)  
Keyword(1) FPGA architecture  
Keyword(2) configuration  
Keyword(3) partial configuration  
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1st Author's Name Tetsuo Hironaka  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
2nd Author's Name Naoki Hirakawa  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
3rd Author's Name Masanori Yoshihara  
3rd Author's Affiliation Hiroshima City University/Renesas Technorogy Corp. (Hiroshima City Univ./Renesas Technorogy Corp.)
4th Author's Name Kazuya Tanigawa  
4th Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
5th Author's Name Masayuki Sato  
5th Author's Affiliation Taiyo Yuden Co., Ltd. (Taiyo Yuden Co., Ltd.)
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Speaker Author-1 
Date Time 2008-10-31 11:15:00 
Presentation Time 60 minutes 
Registration for CPSY 
Paper # CPSY2008-31 
Volume (vol) vol.108 
Number (no) no.273 
Page pp.13-18 
#Pages 6 
Date of Issue 2008-10-24 (CPSY) 

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