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Paper Abstract and Keywords
Presentation 2008-11-17 15:40
Coarse-Grained Reconfigurable Architecture with Flexible Reliability
Younghun Ko, Dawood Alnajjar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye (Osaka Univ.) VLD2008-73 DC2008-41
Abstract (in Japanese) (See Japanese page) 
(in English) Acceptable soft error rate on a VLSI chip varies depending on applications and operating environment so that recent VLSI designers concern reliability specification. In this paper, we propose a novel coarse-grained dynamically reconfigurable architecture, which offers flexible reliability. Introducing a notion of cluster cell, which comprises four execution modules, as a basic element of the proposed architecture, four operation modes (TMR, DMR, SMS, and SMM) can be realized with different redundancy and reliability levels. In the TMR operation mode, which attains the highest reliability level, outputs of three execution modules are voted inside of a cluster cell, making it possible to perform an error recovery without any rollback operations. Evaluation of soft error rates demonstrates that four different reliability levels can be achieved by the proposed architecture. The area of additional circuits to provide flexible reliability accounts for 30.5% of the proposed coarse-grained reconfigurable device.
Keyword (in Japanese) (See Japanese page) 
(in English) reliability / soft error / coarse-grained / reconfigurable architecture / TMR / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 299, DC2008-41, pp. 79-84, Nov. 2008.
Paper # DC2008-41 
Date of Issue 2008-11-10 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2008-73 DC2008-41

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2008-11-17 - 2008-11-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu Science and Research Park 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2008 ―New field of VLSI design― 
Paper Information
Registration To DC 
Conference Code 2008-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Coarse-Grained Reconfigurable Architecture with Flexible Reliability 
Sub Title (in English)  
Keyword(1) reliability  
Keyword(2) soft error  
Keyword(3) coarse-grained  
Keyword(4) reconfigurable architecture  
Keyword(5) TMR  
Keyword(6)  
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Keyword(8)  
1st Author's Name Younghun Ko  
1st Author's Affiliation Osaka University (Osaka Univ.)
2nd Author's Name Dawood Alnajjar  
2nd Author's Affiliation Osaka University (Osaka Univ.)
3rd Author's Name Yukio Mitsuyama  
3rd Author's Affiliation Osaka University (Osaka Univ.)
4th Author's Name Masanori Hashimoto  
4th Author's Affiliation Osaka University (Osaka Univ.)
5th Author's Name Takao Onoye  
5th Author's Affiliation Osaka University (Osaka Univ.)
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Speaker Author-1 
Date Time 2008-11-17 15:40:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # VLD2008-73, DC2008-41 
Volume (vol) vol.108 
Number (no) no.298(VLD), no.299(DC) 
Page pp.79-84 
#Pages 6 
Date of Issue 2008-11-10 (VLD, DC) 

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